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US 2004/0168098 A1Published application
Microcomputer using a shared counter
AssigneeDenso Corporation
InventorsToshihiko Matsuoka, Yukari Ishiguro, Hideaki Ishihara
Life of this patent
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Abstract
In a microcomputer, a watch-dog timer and a sleep control timer share a counter in their signal generating circuits. In a normal operation mode, an AND gate is in a signal passing state and a reset signal RST can be outputted. In a sleep mode, another AND gate is in a signal passing state and a wake-up signal WKUP can be outputted.
Claims10
A microcomputer comprising:
- a CPU;
- a watch-dog timer for outputting an abnormality detection signal when a clear signal input from the CPU stops over a predetermined supervisory time;
- a sleep control timer for outputting a recovery command signal for recovering the CPU to a normal operation mode when a predetermined recovery time passes after the CPU changes to a low power-consumption mode;
- a common counter for counting an operation clock inputted in both the low power-consumption mode and the normal operation mode, a count value of the common counter being cleared based on the clear signal input;
- a supervisory time register for holding a count setting value of the operation clock according to the predetermined supervisory time;
- a recovery time register for holding a count setting value of the operation clock according to the predetermined recovery time;
- a supervisory comparing means which is activated in the normal operation mode and outputs the abnormality detection signal based on a result of comparison between the count value of the common counter and the count setting value of the supervisory time register;
- and
- a recovery comparing means which is activated in the low power-consumption mode and outputs the recovery command signal based on a result of comparison between the count value of the common counter and the count setting value of the recovery time register.
6 more elements
Dependencies are inferred from the claim text.