Instruction rollback processor system, an instruction rollback method and an instruction rollback program
AssigneeKabushiki Kaisha Toshiba
InventorTatsuo Teruyama
Life of this patent
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Abstract
An instruction rollback processor system according to the present invention is provided. The instruction rollback processor system includes: an instruction window buffer storing a plurality of instructions not yet executed and are arranged in a predetermined order; a multiplexer receiving an output of the instruction window buffer; and a rollback unit connected between the output side of the multiplexer and another input of the multiplexer.
Claims12
An instruction rollback processor system comprising:
- an instruction window buffer, storing a plurality of instructions not yet executed and are arranged in a predetermined order;
- a multiplexer receiving an output of the instruction window buffer;
- and a rollback unit connected between the output side of the multiplexer and another input of the multiplexer.
An instruction rollback processor method, comprising:
- rollbacking by rotating using a rollback unit, an instruction not yet executed loop-wise and by holding the instruction during an occurrence of a cache miss;
- repeating the rollbacking when the cache miss is not solved and the rollbacking is not completed normally;
- and
- an instruction re-issue step of issuing a rollback control signal to a multiplexer and issuing an instruction that is not yet executed from an instruction window buffer when the rollbacking is normally completed.
An instruction rollback method implemented by an instruction rollback processor system having an instruction window buffer storing a plurality of instructions that are not yet executed and are arranged in a predetermined order, a multiplexer having an input side and an output side and inputs an output of the instruction window buffer, and a rollback unit connected to the multiplexer, the output of the rollback unit is connected to another input of the multiplexer, comprising:
- a rollbacking by selecting the input side of the rollback unit when rolling back an instruction that is not yet executed;
- and
- re-issuing an instruction by selecting the input from the instruction window buffer when rolling back an instruction that is not yet executed.
An instruction rollback processor method, comprising:
- executing an instruction that is not yet executed and that is issued from an instruction window buffer;
- driving a cache refill circuit when a cache miss occurs, inactivating a load instruction and subsequent instructions in pipeline registers, and freezing the instruction window buffer in the state of the occurrence of the cache miss;
- returning to inactivating the load instruction and subsequent instructions when the operation of the cache refill circuit has been completed and a load instruction is positioned at a position just before the occurrence of the cache miss;
- rotating loop-wise an issued instruction issued from the instruction window buffer and holding the issued instruction when the operation of the cache refill circuit is not completed;
- and
- rotating loop-wise the issued instruction when the operation of the cache refill circuit has been completed and the load instruction is not positioned at the position just before the occurrence of the cache miss.
An instruction rollback program for an instruction rollback processor system, which executes an algorithm comprising:
- instructions configured to execute an instruction that is not yet executed and that is issued from an instruction window buffer;
- instructions configured to drive a cache refill circuit when a cache miss occurs, inactivating a load instruction and subsequent instructions within pipeline registers, and freezing the instruction window buffer in the state of the occurrence of the cache miss;
- instructions configured to return to the instruction configured to inactivate the load instruction and subsequent instructions when the operation of the cache refill circuit has been completed and the load instruction is positioned at a position just before the occurrence of the cache miss;
- instructions configured to rotate loop-wise issued instructions issued from the instruction window buffer and holding the issued instructions when the operation of the cache refill circuit is not completed;
- and
- instructions configured to rotate loop-wise the issued instructions when the operation of the cache refill circuit has been completed and the load instruction is not positioned at the position just before the occurrence of the cache miss.
Dependencies are inferred from the claim text.