Input pipeline registers for a node in an adaptive computing engine
AssigneeQuickSilver Technology, Inc.
InventorAmit Ramchandran
Life of this patent
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Abstract
Input pipeline registers are provided at inputs to functional units and data paths in a adaptive computing machine. Input pipeline registers are used to hold last-accessed values and to immediately place commonly needed constant values, such as a zero or one, onto inputs and data lines. This approach can reduce the time to obtain data values and conserve power by avoiding slower and more complex memory or storage accesses. Another embodiment of the invention allows data values to be obtained earlier during pipelined execution of instructions. For example, in a three stage fetch-decode-execute type of reduced instruction set computer (RISC), a data value can be ready from a prior instruction at the decode or execute stage of a subsequent instruction.
Claims16
A computational unit in an adaptable computing engine, wherein the computational unit includes a clock signal for determining a processor cycle, the computational unit comprising
- one or more functional units coupled by a bus, wherein the one or more functional units include functional unit inputs;
- at least one register coupled between the bus and at the input of least one functional unit input;
- and
- a control signal for selectively causing the at least one register to hold a data value from the bus for one or more processor cycles.
A method for providing data in a computational unit in an adaptable computing engine, the method comprising
- including registers at inputs to functional units, wherein the registers are coupled to a bus for obtaining data from the bus;
- including a control signal for selectively causing the registers to hold a data value from the bus for one or more processor cycles.
An apparatus for providing a data value in a computational unit in an adaptable computing engine, wherein the computational unit includes a multi-stage execution pipeline, the apparatus comprising
- one or more functional units coupled by a bus, wherein the one or more functional units include functional unit inputs;
- at least one input register coupled between the bus and at least one functional unit input;
- and
- a data path from an input register to a given stage in the execution pipeline so that a value provided by the register is available for use at a time of execution of the given stage.
A method for providing a data value in a computational unit in an adaptable computing engine, wherein the computational unit includes a multi-stage pipeline, the method comprising
- coupling one or more functional units to a bus, wherein the one or more functional units include functional unit inputs;
- coupling at least one register between the bus and at least one functional unit input;
- and
- providing a data path from a register to a given stage in the execution pipeline so that a value provided by the register is available for use at a time of execution of the given stage.
Dependencies are inferred from the claim text.