Pipelined architecture with separate pre-fetch and instruction fetch stages

A pipelined central processing unit (CPU) comprising:

• a pre-fetch (PF) stage for performing branch prediction, the PF stage comprising a PF address (PFA) register for storing the address of an instruction being processed by the PF stage;
• an instruction fetch (IF) stage for fetching instructions that are to be later processed by an execution (EX) stage, the IF stage comprising an IF address (IFA) register for storing the address of an instruction to be fetched for later execution, and accepting a branch prediction result from the PF stage;
• and
• address register control (ARC) circuitry for setting the contents of the PFA and the IFA, the ARC utilizing the branch prediction result held in the IF stage to determine the contents of the PFA and the IFA;
• wherein if the branch prediction result held in the IF stage predicts no branching, then the ARC sets a next address of the PFA to be sequentially after a current address of the PFA and a next address of the IFA be the current address of the PFA, and if the branch prediction result held in the IF stage predicts a branch, then the ARC sets the next address of the PFA to be sequentially after a predicted branch address and the next address of the IFA be the predicted branch address.