Simultaneous Multi-Threading Processor circuits and computer program products configured to operate at different performance levels based on a number of operating threads and methods of operating

A Simultaneous Multi-Threading (SMT) Processor comprising:

• a performance level control circuit configured to provide a performance level to processing circuits in the SMT processor based on a number of threads currently operated by the SMT processor.

A Simultaneous Multi-Threading (SMT) Processor comprising:

• a thread management circuit configured to assign processing circuits associated with the SMT processor to threads operated in the SMT processor as the threads are created;
• and
• a performance level control circuit configured to provide one of a plurality of performance levels to the processing circuits based on a number of threads currently operated by the SMT processor compared to at least one threshold value.

A cache memory associated with a Simultaneous Multi-Threading (SMT) processor, the cache memory including a tag memory and a data memory accessed either concurrently or the data memory is accessed subsequent to the tag memory based on a number of threads currently operated by the SMT processor.

A method of operating a Simultaneous Multi-Threading (SMT) processor comprising:

• providing a performance level to at least one processing circuit based on a number of threads currently operated by the SMT processor.

A Simultaneous Multi-Threading (SMT) processor comprising:

• means for providing a performance level to at least one processing circuit based on a number of threads currently operated by the SMT processor.

A computer program product for operating a Simultaneous Multi-Threading (SMT) processor comprising:

• a computer readable medium having computer readable program code embodied therein, the computer readable program product comprising:
• computer readable program code configured to provide a performance level to at least one processing circuit in the SMT processor based on a number of threads currently operated by the SMT processor.