Loading patent…
AssigneeIntel Corporation
InventorsBrian M. Collins, Dick Reohr
Estimating the term…
A method and apparatus for non-contiguous translation protection table that includes one or more first registers, two or more second registers, an address translator, and a detector. Each first register contains a value denoting a size of each of two or more blocks of memory. Each second register contains a value denoting the starting physical address of an associated one of the two or more blocks of memory. The address translator receives a virtual address and translates the virtual address to a physical address of one of the two or more blocks of memory. The detector detects whether the received virtual address is outside of the range of the two or more blocks of memory. The blocks of memory may be translation protection tables that reside in physically non-contiguous memory locations.
An apparatus comprising:
A system comprising:
A method comprising:
A computer-readable medium having computer-executable instructions for performing a method comprising:
Dependencies are inferred from the claim text.