US 2004/0168036 A1 · Method and apparatus for adjusting the performance of a synchronous memory system

Abstract

A method and apparatus for adjusting the performance of a memory system is provided. A memory control device comprises a master device including a frequency detector, a memory channel, and a memory device coupled to the master device via the memory channel. The memory device includes a decoder designed to receive a control signal from the master device. A clock recovery and alignment circuit receives the control signal from the decoder and adjusts the operating frequency of the memory device in response to the control signal.

Claims35

Dependent claims

A method for controlling performance of a memory system, the memory system including a master device and slave memory devices coupled to the master device via a memory channel, the method comprising the steps of:

sending an operating information from the master device via the memory channel to at the slave memory devices;
receiving the operating information and storing it in at least one of the slave memory devices;
and
using the operating information to tune circuitry within the slave memory devices to improve the performance of the memory system.

1 more element

Dependencies are inferred from the claim text.

Facts

Application

10/386,210Filed 10 Mar 2003

Priority

10 Oct 1997

Published

26 Aug 2004

Term ends

Not estimatedThe source records don’t support an estimate.

Classification7 codes

G11C 7/1048
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data bus control circuits, e.g. precharging,…
G06F 13/1689
Details of memory controller: synchronisation and timing concerns
G11C 7/22
Arrangements for writing information into, or reading information out from, a digital store: read-write [R-W] timing or clocking circuits;…
G11C 7/222
Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management: clock generating, synchronizing or…

Family

Application08/948,774Continuation · filed 10 Oct 1997

Application10/051,957Continuation · filed 18 Jan 2002

Application10/386,210Continuation · filed 10 Mar 2003

US 2002/0087820 A1Published application

US 6,513,103 B1Related patent

US 6,553,452 B2Related patent

US 7,149,856 B2Related patent

US 2004/0168036 A1This patent

From the US filing history. Foreign family members aren’t listed.

Method and apparatus for adjusting the performance of a synchronous memory system

Life of this patent

Method and apparatus for adjusting the performance of a synchronous memory system

Life of this patent

Abstract

Claims35