Pipeline scalable architecture for high density and high speed content addressable memory (CAM)
OwnerXiaohua Huanginventor
Life of this patent
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Abstract
The Inventions divide the entire CAM block into many identical small sub-block and then symmetrically place them. Divide them into four quadruple, then in each quadruple place them in equal row and column. the address, data bus are routed symmetrically into the center first and then to each quadruple, then to each column in each quadruple and then into each sub-block. Address decoding, Content matching in each sub-block, priority encoding, hit result reading out in different cycle. In this way, each cycle time can be short, and the throughput of CAM matching can be increased. In this design the power can be reduced. Each sub-blocks are identical. The logical interface among sub-block in each column are identical. The design is scalable.
Claims18
The LARGE CAM or TCAM are divided into 2N same size small sub-block and each small sub-block has its own address decoding and priority encoding function.
The small sub-block are placed symmetrically around the center of the CAM unit.
The small sub-block are equally placed in the each quadruples.
In each quadruples, The sub-block are placed as a matrix, like 8 column and 8 row.
The bus of address and Data to write or match are routed to the mid-point at each Side and then sent to the center of the chip or CAM unit.
The writing data are sent to the right side or left side based on the first level decoding, then sent to the particular column based on the second level decoding, then are sent to the particular sub-block based on the third level decoding.
only the reading out data take the data bus at different level, say, only the particular sub-block in each column will take the bus and among 8 column, only the column in which there is a reading sub-block will take the data bus.
On search or match case, only the highest priority hit sub-block will take the Match Address result bus on that column among the 8 sub-block, then only the highest priority hit column Will take the Match Address result bus among the 8 column.
The data writing can be pipe lined into multi-cycle.
The address decoding of data writing can be divided into multi-cycle.
For Reading data, the address decoding can be divided into multi-cycle.
The data read out can be divided into multi-cycle.
the address match or search can be divided into multi-cycle.
the priority encoding can be divided into multi-cycle.
The each sub-block are independent sub-block with its own address decoding and write and read buffer as well as priority encoding.
Each sub-block are identical on the internal design and interface.
the logic interface in each column among each sub-block are identical.
the logic interface among each column for four quadruple are identical.
Dependencies are inferred from the claim text.