Memory device interface
AssigneeMicron Technology, Inc.
InventorKevin J. Ryan
Life of this patent
Estimating the term…
Abstract
An interface device provided on a motherboard, or with a memory control chip set, translates between a controller, intended to communicate with a packet based memory system, and a non-packet based memory system. Communications from a memory controller, intended to directly communicate with a RAMBUS RDRAM memory system, are translated for a memory system which does not comprise RAMBUS RDRAM. The interface device, or integrated circuit, is not located with the memory system. That is, the memory modules do not include the interface circuit. Instead, the interface device is located with the processor motherboard, or with the controller/bridge integrated circuit chip set, such that it is electrically located between a controller and main memory sockets.
Claims24
A processing system comprising:
- a memory controller adapted to issue and receive commands in a packet based protocol;
- a cache memory;
- a plurality of memory modules comprising SDRAM devices;
- and
- a single interface device located with the memory controller such that the interface device is not located on the memory modules, the interface device adapted to translate packet based protocol command and data signals from the memory controller into an SDRAM protocol, and the interface device adapted to translate data signals received from the memory module into packet based protocol data.
A processing system comprising:
- a memory controller adapted to issue and receive commands in a packet based protocol;
- a cache memory;
- a plurality of memory modules comprising SDRAM devices, the plurality of memory modules each being located in a memory socket;
- and
- a single interface device located between the memory controller and the memory sockets, the interface device adapted to translate packet based protocol command and data signals from the memory controller into an SDRAM protocol, and the interface device adapted to translate data signals received from the memory module into packet based protocol data.
A processing system comprising:
- a memory controller adapted to issue and receive commands in a packet based protocol;
- a cache memory;
- a plurality of memory modules comprising SDRAM devices, the plurality of memory modules each being located in a memory socket;
- and
- a single interface device located between the memory controller and the memory sockets, the interface device adapted to translate packet based protocol command and data signals from the memory controller into an SDRAM protocol, the interface device comprises:
- a write demultiplex circuit adapted to convert data received on N data lines from the memory controller to M×N data lines;
- a read multiplex circuit adapted to convert received data on the M×N data lines from the memory module to the N data lines;
- and
- a command disassembler adapted to convert packet based commands from the memory controller into row/column based commands.
A processing system comprising:
- a memory controller adapted to issue and receive commands in a packet based protocol;
- a cache memory;
- a plurality of memory modules each comprising column/row protocol based devices, the memory modules are located in in-line memory module sockets;
- and
- a single interface device located between the memory controller and the in-line memory module sockets, the interface device adapted to translate packet based protocol command and data signals from the memory controller into the column/row protocol, and the interface device adapted to translate data signals received from the memory modules into packet based protocol data.
A processing system motherboard comprising:
- a memory controller adapted to issue and receive commands in a packet based protocol;
- a cache memory;
- and
- a single interface device adapted to translate packet based protocol command and data signals from the memory controller into a column/row protocol, and adapted to translate data signals received from the plurality of memory modules that are located external to the motherboard into the packet based protocol data.
A processing system comprising:
- a processor;
- and
- a chip set, comprising:
- a memory controller adapted to issue and receive commands in a packet based protocol;
- a cache memory coupled to the processor, and
- a single interface device adapted to translate packet based protocol command and data signals from the memory controller into a column/row protocol, and adapted to translate data signals received from the plurality of memory modules, each of the memory modules being separately detachable from the interface device into the packet based protocol data.
A processing system comprising:
- a processor;
- a cache memory coupled to the processor;
- a plurality of memory modules comprising SDRAM devices, the plurality of memory modules each being located in a memory socket;
- a chip set, comprising:
- a memory controller adapted to issue and receive commands in a packet based protocol;
- and
- a single interface device located between the memory controller and the memory sockets, the interface device adapted to translate packet based protocol command and data signals from the memory controller into an SDRAM protocol.
Dependencies are inferred from the claim text.