Data access in a processor
AssigneeAlphamosaic Limited
InventorsStephen Barlow, Timothy Ramsdale, Robert Swann, Neil Bailey, David Plowman
Life of this patent
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Abstract
A data processor comprising: a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.
Claims13
A data processor comprising a register memory comprising an array of memory cells, each cell being addressable by means of an instruction specifying a pair of coordinates that identify the cell in the array.
A data processor as claimed in any preceding claim, wherein:
- the array is an orthogonal array having two dimensions and has an extent of X cells in a first dimension and an extent of Y cells in a second direction;
- each cell is addressable by coordinates that identify the index of the cell in the array in the first and second directions;
- and the data processor is arranged to interpret an instruction referencing by a coordinate B in the second dimension a cell located outside the bounds of the array in the second dimension cell as specifying a cell having a coordinate (B−Y) or (B+Y) in the second dimension.
A data processor as claimed in any preceding claim, wherein each cell of the array is capable of storing 8 or more bits.
A data processor as claimed in any preceding claim, wherein the register memory and the processing unit are arranged on the same integrated circuit.
A data processor as claimed in any preceding claim, wherein the register memory comprises a memory access port arranged to:
- receive from the data processor a call identifying a plurality of cells by means of a first call part specifying a pair of coordinates that identify a first cell in the array, and a second call part that identifies the configuration of the plurality of cells relative to the first cell;
- to interpret the call to identify the cells in the array referenced by the call;
- and
- return to the data processor the contents of those cells.
A data processor as claimed in any preceding claim, wherein the array is formed of an array of single bit storage units extending in two dimensions each storage unit being located on a row in the first dimension and a column in the second dimension;
- a first set of word lines extending in the first dimension, each word line of the first set of word lines running along a row and being connected to each storage unit located in that row for enabling those storage units for reading or writing;
- a second set of word lines extending in the second dimension, each word line of the second set of word lines running along a column and being connected to each cell located in that column for enabling those storage units for reading or writing;
- and
- a set of bit lines running diagonally to the word lines, each bit line being connected to one storage unit in each row and to one storage unit in each column for carrying data to or from the respective storage unit.
A data processor as claimed in any preceding claim, wherein:
- the array extends in two dimensions and the memory cells of the array are located on rows in the first dimension and columns in the second dimension;
- and
- the data processor is arranged to interpret one form of second instruction part as specifying at least one bit of each cell other than the cell specified in the first instruction part that:
- i. is in the same row as the cell specified in the first instruction part or is in a row adjacent to that row;
- and
- ii. is in the same column as the cell specified in the first instruction part or is in a column adjacent to that column.
A data processor as claimed in any preceding claim, wherein:
- the array extends in two dimensions and the memory cells of the array are located on rows in the first dimension and columns in the second dimension;
- and
- the data processor is arranged to interpret one form of second instruction part as specifying a first group of cells all of which are located in the same row but in different columns, and to interpret a second form of second instruction part as specifying a first group of cells all of which are located in the same column but in different rows.
A data processor substantially as herein described with reference to the accompanying drawings.
Dependencies are inferred from the claim text.