Synchronous flash memory with concurrent write and read operation
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
Estimating the term…
Abstract
A synchronous flash memory includes an array of non-volatile memory cells. The memory array is arranged in rows and columns, and can be further arranged in addressable blocks. Data communication connections are used for bi-directional data communication with an external device(s), such as a processor or other memory controller. A write latch is coupled between the data buffer and the memory array to latch data provided on the data communication connections. The memory can write data to one location, such as a memory array block, while data is read from a second location, such as a second memory array block. The write and read operations are performed on a common addressable row of the array blocks.
Claims11
A processing system comprising:
- first and second processors;
- and
- a non-volatile memory coupled to the first and second processors, the non-volatile memory comprises,
- an array of non-volatile memory cells arranged in a plurality of addressable banks,
- a data latch coupled to the array to store write data, and
- read/write circuitry coupled to the array, wherein the read/write circuitry writes first data provided by the first processor to a first one of the plurality of addressable banks and simultaneously reads second data from a second one of the plurality of addressable banks and provides the second data to the second processor.
A method of operating a non-volatile memory device comprising:
- receiving first data from a first external processor coupled to the memory;
- storing the first data in a write latch;
- writing the first data from the write latch to a first location in a memory array of the non-volatile memory device;
- substantially simultaneously reading second data from a second location in the memory array of the non-volatile memory device;
- and
- outputting the second data to a second external processor coupled to the memory device.
A non-volatile memory comprising:
- an array of non-volatile memory cells arranged in a plurality of addressable banks;
- and
- read/write circuitry coupled to the array, wherein the read/write circuitry writes first data to a first one of the plurality of addressable banks and simultaneously reads second data from a second one of the plurality of addressable banks, wherein the read/write circuitry receives the first data from a first external processor and provides the second data to a second external processor.
A method of operating a non-volatile memory comprising:
- providing first data to the non-volatile memory from a first external processor;
- writing the first data to a first bank location in a memory array of the non-volatile memory;
- substantially simultaneously reading second data from a second bank location in the memory array of the non-volatile memory;
- and
- outputting the second data to a second external processor.
Dependencies are inferred from the claim text.