Memory address decoding method and related apparatus by bit-pattern matching
AssigneeVIA Technologies, Inc.
InventorJacky Tsai
Life of this patent
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Abstract
An address decoding method and related apparatus for deciding which section of a memory device a given address belongs. The memory device has a plurality of sections, each section has a plurality of memory units, and each memory unit has a unique address. The method includes: comparing some specific bits of the given address with predetermined values for deciding which section the given address belongs.
Claims18
A memory address decoding method for determining if a given address is located in one of a plurality of sections, each section having a plurality of memory units and each memory unit having a unique corresponding address, the corresponding addresses using the binary system, the method comprising:
- building at least one bit-pattern for each section from the corresponding addresses respectively;
- and
- comparing if at least one comparative bit of the given address matches any of the bit-patterns so as to determine that the given address is located in one of the sections based on the comparison.
A control circuit of memory address decoding for determining whether a given address is located in one of a plurality of sections, each section having a plurality of memory units and each memory unit having a unique corresponding address, the corresponding addresses using the binary system, the control circuit comprising:
- a pattern calculation module for building at least one bit-pattern for each section based on the corresponding addresses;
- an access module for receiving the given address;
- and
- a comparing module for sending a plurality of comparison signals after comparing at least one comparative bits of the given address with each bit-pattern provided by the pattern calculation module and both of them matching.
Dependencies are inferred from the claim text.