US 2004/0167992 A1Published application

Method and apparatus for implementing receive queue for packet-based communications

AssigneeInternational Business Machines Corporation

InventorsMichael Joseph Carnevale, Daniel Frank Moertl

Life of this patent

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Abstract

A receiver for an InfiniBand network contains a buffer and a control memory. A set of pointers for receive queues in the buffer is maintained in the control memory. Two independent queues exist for incoming messages from a given source, one for writes and the other for reads. The receiver controls the various queue pointers to generate appropriate acknowledgments and negative acknowledgment messages, and to transfer data as required to and from the host over an internal bus. Preferably, the receiver delays acknowledging certain write requests if requests are pending on the read queue. Preferably, the control memory and the major control functions of the receiver are implemented in hardware on a ASIC chip.

Claims17

Dependent claims

An I/O adapter for a packet-switched network, comprising:

a buffer memory;
a packet disassembler receiving request packets from a requester over said network and building blocks from said packets in queues in said buffer memory, said request packets including packets of a first type requesting that data be sent to the requester and packets of a second type containing data sent by the requester;
wherein said packet disassembler places blocks from packets of said first type in a first queue and blocks from packets of said second type in a second queue;
wherein said packet disassembler detects an out-of-sequence packet and, responsive thereto, builds a negative acknowledge (NAK) block in said first queue;
a control memory for containing state data, said state data including a plurality of queue pointers, said queue pointers pointing to locations in said first and second queues;
a receive queue sequencer, said receive queue sequencer determining when to send acknowledgment packets to said requester from said state data in said control memory, wherein packets are acknowledged in the order received;
and
a packet builder which builds and sends acknowledge packets responsive to said receive queue sequencer.

5 more elements

A method of interfacing with a packet-switched network, comprising the steps of:

receiving request packets from a requester over said network and building blocks from said packets in queues in a buffer memory, said request packets including packets of a first type requesting that data be sent to the requester and packets of a second type containing data sent by the requester;
placing blocks form packets of said first type in a first queue in said buffer memory and blocks from packets of said second type in a second queue in said buffer memory;
detecting out-of-sequence packets and, responsive thereto, building negative acknowledgment (NAK) blocks in said first queue;
maintaining state data for said first and second queues;
determining when to send acknowledgment packets to said requester from said state data, wherein packets are acknowledged in the order received, and wherein acknowledgments for at least some packets of said second type are coalesced with acknowledgments for other packets;
and
building and sending acknowledge packets responsive to said step of determining when to send acknowledgment packets.

4 more elements

Dependencies are inferred from the claim text.

Facts

Application: 10/374,256Filed 26 Feb 2003
Published: 26 Aug 2004
Term ends: Not estimatedThe source records don’t support an estimate.

Classification7 codes

H04L 1/1607
In which the return channel carries supervisory signals, e.g. repetition request signals: details of the supervisory signal
H04L 49/90
Packet switching elements: buffering arrangements
H04L 49/901
Buffering arrangements: using storage descriptor, e.g. read or write pointers
H04L 49/9063
Buffering arrangements: intermediate storage in different physical parts of a node or terminal