Overflow detection system for multiplication

Abstract

A math device has a multiplier and an overflow detector. The multiplier multiplies an n-bit input with an m-bit input and produces a reduced width output without producing an intervening data file having a width greater than or equal to n+m. The overflow detector determines if the reduced width output eliminates non-redundant bits. According to a second aspect, the overflow detector determines when the product of the m-bit input and the n-bit input would exceed o-bits, where o<(m+n), the overflow detector having a first overflow unit provided in parallel to the multiplier, and a second overflow unit provided in series with the multiplier. According to a third aspect, the overflow detector has a comparator provided on a critical timing path, and the comparator requires only a review of 4 bits.

Dependencies are inferred from the claim text.