Method and system for generating an atpg model of a memory from behavioral descriptions

A method as recited in Claim 4 wherein said plurality of ATPG memory primitives comprises:

• a memory primitive;
• an address bus primitive;
• a data bus primitive;
• a read port primitive;
• and
• a plurality of macro output primitives.

A method as recited in Claim 4 wherein said memory is a random access memory (RAM) and wherein said plurality of ATPG memory primitives comprises:

• an address bus primitive;
• a memory primitive for coupling to receive addresses from said address bus primitive;
• a data bus primitive for coupling to provide data to said memory primitive;
• a read port primitive for coupling to receive data from said memory primitive and for coupling to receive addresses from said address bus primitive;
• and
• a plurality of macro output primitives for coupling to said read port.

A method as recited in Claim 4 wherein said plurality of ATPG memory primitives comprises:

• a memory primitive;
• a compare port primitive;
• and
• a plurality of macro output primitives.

A method as recited in Claim 4 wherein said memory is a content addressable memory (CAM) and wherein said plurality of ATPG memory primitives comprises:

• a memory primitive;
• a compare port primitive for coupling to receive first data from a data bus primitive and for coupling to said receive second data from said memory primitive, wherein said compare port primitive is for comparing said first data and said second data and for supplying an address of said memory primitive provided said first data matches said second data;
• and
• a plurality of macro output primitives for outputting said address of said memory primitive.

A computer readable medium as recited in Claim 16 wherein said plurality of ATPG memory primitives comprises:

• a memory primitive;
• an address bus primitive;
• a data bus primitive;
• a read port primitive;
• and
• a plurality of macro output primitives.

A computer readable medium as recited in Claim 16 wherein said memory is a random access memory (RAM) and wherein said plurality of ATPG memory primitives comprises:

• an address bus primitive;
• a memory primitive for coupling to receive addresses from said address bus primitive;
• a data bus primitive for coupling to provide data to said memory primitive;
• a read port primitive for coupling to receive data from said memory primitive and for coupling to receive addresses from said address bus primitive;
• and
• a plurality of macro output primitives for coupling to said read port.

A computer readable medium as recited in Claim 16 wherein said memory is a content addressable memory (CAM) and wherein said plurality of ATPG memory primitives comprises:

• a memory primitive;
• a compare port primitive for coupling to receive first data from a data bus primitive and for coupling to said receive second data from said memory primitive, wherein said compare port primitive is for comparing said first data and said second data and for supplying an address of said memory primitive provided said first data matches said second data;
• and
• a plurality of macro output primitives for outputting said address of said memory primitive.

A computer controlled electronic design automation system comprising:

• a processor;
• a display device;
• a bus coupled to said processor;
• and
• a computer readable medium coupled to said bus and having stored therein computer readable program code for causing said electronic design automation system to perform a method of constructing a structural model for a memory for use in ATPG (Automatic Test Pattern Generation), said method comprising the steps of:
• (a)accessing a simplified behavioral model of said memory from said computer readable medium wherein said simplified behavioral model is described in a behavioral hardware description language and wherein said simplified behavioral model is generated based on a simulation model of said memory;
• and
• (b)automatically translating said simplified behavioral model into said structural model of said memory and storing said structural model into said computer readable medium, wherein said structural model comprises a plurality of ATPG memory primitives.

An electronic design automation system as recited in Claim 28 wherein said plurality of ATPG memory primitives comprises:

• a memory primitive;
• an address bus primitive;
• a data bus primitive;
• a read port primitive;
• and
• a plurality of macro output primitives.

An electronic design automation system as recited in Claim 28 wherein said memory is a random access memory (RAM) and wherein said plurality of ATPG memory primitives comprises:

• an address bus primitive;
• a memory primitive for coupling to receive addresses from said address bus primitive;
• a data bus primitive for coupling to provide data to said memory primitive;
• a read port primitive for coupling to receive data from said memory primitive and for coupling to receive addresses from said address bus primitive;
• and
• a plurality of macro output primitives for coupling to said read port.

An electronic design automation system as recited in Claim 28 wherein said memory is a content addressable memory (CAM) and wherein said plurality of ATPG memory primitives comprises:

• a memory primitive;
• a compare port primitive for coupling to receive coupled first data from a data bus primitive and for coupling to said receive second data from said memory primitive, wherein said compare port primitive is for comparing said first data and said second data and for supplying an address of said memory primitive provided said first data matches said second data;
• and
• a plurality of macro output primitives for outputting said address of said memory primitive.