US 2004/0166823 A1 · Control interface scheme for wireless communication chipsets

Abstract

A control interface scheme provides for communicating control information between integrated circuits (ICs) in a wireless communication chipset. A serial 3-wire bus is configured to communicate a series of control words assembled on a digital IC to an analog IC prior to a data portion of a frame used by the wireless communication chipset in communicating data. The control words include control settings for use by the analog IC during the data portion of the frame. The control settings, which are stored in registers on the analog IC, include gain settings for two receivers and a transmitter, as well as phase lock loop (PLL) control information and power management information. Several timing signals generated on the digital IC are used by the analog IC during the data portion of the frame to select among the registers to obtain the appropriate control settings at the appropriate times. By sending all such control settings to the analog IC prior to the data portion of the frame, the PLLs on the analog IC are not disturbed.

Claims36

Dependent claims

A method of handling control information in a first integrated circuit (IC) used for wireless communications, comprising the steps of:

receiving in the first IC a plurality of control settings that were generated in a second IC and communicated across a bus from the second IC to the first IC prior to a data portion of a frame used by the first and second ICs in communicating data;
and
receiving in the first IC one or more timing signals that are generated in the second IC and that are for use during the data portion of the frame for selecting certain ones of a plurality of registers in the first IC that are used for storing the plurality of control settings.

A method of handling control information in a first integrated circuit (IC) used for wireless communications, comprising the steps of:

receiving in the first IC a first control word and a second control word that were assembled in a second IC and communicated across a bus from the second IC to the first IC prior to a data portion of a frame used by the first and second ICs in communicating data, wherein the first control word includes a plurality of first receive gain settings for a first receiver amplifier, and the second control word includes a plurality of transmit gain settings for a transmitter amplifier;
and
receiving in the first IC one or more timing signals that are generated in the second IC and that are used during the data portion of the frame for selecting certain ones of a plurality of registers in the first IC that are used for storing the plurality of first receive gain settings and the plurality of transmit gain settings.

Dependencies are inferred from the claim text.

Control interface scheme for wireless communication chipsets

Life of this patent

Control interface scheme for wireless communication chipsets

Life of this patent

Abstract

Claims36