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US 2004/0166659 A1Published application
Top layers of metal for high performance IC's
AssigneeMegic Corporation
InventorsMou-Shiung Lin, Jin-Yuan Lee
Life of this patent
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Abstract
The present invention adds one or more thick layers of polymer dielectric and one or more layers of thick, wide metal lines on top of a finished semiconductor wafer, post-passivation. The thick, wide metal lines may be used for long signal paths and can also be used for power buses or power planes, clock distribution networks, critical signal, and re-distribution of I/O pads for flip chip applications. Photoresist defined electroplating, sputter/etch, or dual and triple damascene techniques are used for forming the metal lines and via fill.
Claims63
A method for forming a top metallization system for high performance integrated circuits, comprising:
- providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines;
- wherein said first openings are as small as 0.1 um;
- and
- forming said top metallization system in said first openings and over said passivation layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a thickness substantially greater than said first metal lines, wherein the top metallization system connects portions of said interconnecting metallization structure to other portions of said interconnecting metallization structure.
1 more element
A method for forming a top metallization system for high performance integrated circuits, comprising:
- providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines;
- depositing a polymer insulating layer over said passivation layer, and forming second openings in said polymer, insulating layer to expose said contact pads, wherein said second openings in said polymer layer are lined up with said first openings in said passivation layer, and the size of said second openings is greater than that of said first openings;
- and
- forming said top metallization system in said first openings and over said passivation layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a thickness substantially greater than said first metal lines, wherein the top metallization system connects portions of said interconnecting metallization structure to other portions of said interconnecting metallization structure.
1 more element
A method for forming a top metallization system for high performance integrated circuits, comprising:
- providing an integrated circuit comprising a plurality of devices formed in and on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines;
- wherein said first openings are as small as 0.1 um;
- and
- forming said top metallization system in said first openings and over said passivation layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a width substantially greater than said first metal lines, wherein the top metallization system connects portions of said interconnecting metallization structure to other portions of said interconnecting metallization structure.
1 more element
A semiconductor device structure, comprising:
- semiconductor devices formed on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines, wherein said first openings are as small as 0.1 um;
- and
- a top metallization system formed in said openings and over said passivation layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a thickness substantially greater than said first metal lines.
A semiconductor device structure, comprising:
- semiconductor devices formed on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines, wherein said first openings are as small as 0.1 um;
- and
- a top metallization system formed in said openings and over said passivation layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a thickness substantially greater than said first metal lines;
- wherein said top metal lines comprise gold (Au) over a titanium tungsten (TiW) underlayer.
1 more element
A semiconductor device structure, comprising:
- semiconductor devices formed on a semiconductor substrate, with an overlaying interconnecting metallization structure connected to said devices and comprising a plurality of first metal lines, and having a passivation layer formed thereover, with first openings in said passivation layer to contact pads connected to said first metal lines, wherein said first openings are as small as 0.1 um;
- and
- a top metallization system formed in said openings and over said passivation layer, connected to said interconnecting metallization structure, wherein said top metallization system comprises a plurality of top metal lines, in one or more layers, having a thickness substantially greater than said first metal lines;
- wherein said top metal lines comprise plated copper (Cu) over a copper seed layer formed over a chromium (Cr) underlayer, and wherein said plated copper is covered with a nickel (Ni) cap layer.
1 more element
Dependencies are inferred from the claim text.