Array architecture and process flow of nonvolatile memory devices for mass storage applications

A non volatile memory, comprising:

• a) flash memory cells organized in rows and columns,
• b) cells in a row are interconnected by a wordline connecting to control gates of said flash memory cells in said row,
• c) cell layout in a column mirrors cell layout in adjacent columns producing a first pair of adjacent columns with drains close together and a second pair of adjacent columns with sources close together,
• d) a bit lines extend full length of said columns, laying between said first pair of adjacent columns and connecting said drains of said first pair of adjacent columns to a sense amplifier,
• e) a source lines extend full length of said columns, laying between said second pair of adjacent columns and connecting said sources of said second pair of adjacent columns to source voltages.

A method to produce an electrically erasable and programmable (EEPROM) for mass storage applications, comprising:

• a) forming a well in a semiconductor substrate,
• b) implanting ions into said well to establish a threshold voltage,
• c) forming a gate isolation layer on top of said substrate,
• d) forming a floating gate structure comprising a first layer of polysilicon with a dielectric insulator thereupon,
• e) forming a sidewall spacer on sides of said floating gate structure,
• f) ion implanting a plurality of drain and source regions in said well using said sidewall spacers as a mask,
• g) removing sidewalls adjacent to said source regions,
• h) double diffusing said source regions,
• i) implanting a source within said source region,
• j) depositing an isolation oxidation on source and drain regions and removing side wall spacers,
• k) growing an interpoly dielectric,
• l) depositing a second layer of polysilicon,
• k) forming a control gate structure from said second layer of polysilicon and covering a plurality of said floating gate structures.