Cmos performance enhancement using localized voids and extended defects
AssigneeInternational Business Machines Corporation
InventorsOmer H. Dokumaci, Dureseti Chidambarrao, Suryanarayan G. Hegde
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Abstract
The speed of CMOS circuits is improved by imposing a longitudinal tensile stress on the NFETs and a longitudinal compressive stress on the PFETs, by implanting in the sources and drains of the NFETs ions from the eighth column of the periodic table and hydrogen and implanting in the sources and drains of the PFETs ions from the fourth and sixth columns of the periodic table.
Claims20
A method of forming an integrated circuit, comprising the steps of:
- preparing a substrate;
- forming a set of transistors including a PFET and an NFET in said substrate;
- performing a first implant in said substrate with species that cause formation of a first type of defect in source and drain locations in the NFET;
- performing a second implant in said substrate with species that cause formation of a second type of defect in source and drain locations in the PFET;
- wherein the first type of defect causes a first type of stress on a channel region of the NFET, and the second type of defect causes a second type of stress on a channel region of the PFET, the first type of stress being different from the second type of stress.
A method of forming an integrated circuit, comprising the steps of;
- preparing a substrate;
- forming a set of transistor gates in NFET and PFET locations in said substrate, said transistor gates having temporary sidewalls;
- performing a defect implant in said substrate in source and drain locations of said NFET and PFET locations in said substrate to generate defects therein;
- removing said temporary sidewalls;
- and
- performing extension and halo implants in the substrate, after said step of removing said temporary sidewalls.
An integrated circuit formed in a semiconductor substrate, comprising:
- a set of PFET and NFET transistors in which at least some of said NFET and PFET transistors have their sources and drains implanted with a substance that produces a stress on the bodies thereof, and in which said NFET transistors have an implant that produces a tensile stress in the bodies of said NFETs and in which said PFET transistors have an implant that produces a compressive stress in the bodies of said PFETs.
Dependencies are inferred from the claim text.