Fractional-N synthesizer with two control words

A fractional frequency synthesizer to provide an output frequency that is a multiple of a reference input frequency, comprising:

• a multiple modulus frequency divider connected to receive the output frequency and dependant upon a modulus factor select one of a plurality of divisors for said output frequency;
• a modulus controller in communication with the multiple modulus frequency divider to control the modulus factor, said modulus controller comprising:
• a first factor input to receive a first digital data word having a first number of bits;
• a second factor input to receive a second digital data word having a second number of bits;
• a gain factor input to receive a gain factor digital data word indicating an integer multiplier for the first digital data word;
• and
• a modulus selection circuit in communication with the first factor input, the second factor input, and the gain factor input to provide a modulus control signal to said modulus divider to select the modulus factor of said modulus divider as a function of a sum of the second digital data word and a product of the first digital data word and the gain factor digital data word.

A method for controlling a divisor modulus factor for a multiple modulus divider incorporated in a fractional frequency synthesizer, comprising the steps of:

• receiving a first factor input having a first number of bits;
• receiving a second factor input having a second number of bits;
• receiving a gain factor input indicating an integer multiplier for the first factor;
• and
• determining said divisor modulus factor for said multiple modulus divider as a function of a sum of the second factor input and a product of the first factor input and the gain factor input.

A apparatus for controlling a divisor modulus factor for a multiple modulus divider incorporated in a fractional frequency synthesizer, comprising the steps of:

• means for receiving a first factor input having a first number of bits;
• means for receiving a second factor input having a second number of bits;
• means for receiving a gain factor input indicating an integer multiplier for the first factor input;
• and
• means for determining said divisor modulus factor for said multiple modulus divider as a function of a sum of the second factor input and a product of the first factor input and the gain factor input.