Format conversion circuit
AssigneeInternational Business Machines Corporation
InventorsHiroaki Kubo, Masahiro Murakami
Life of this patent
Estimating the term…
Abstract
A format conversion circuit 100 includes a FIFO memory 101 for writing and reading video data VD in synchronization with a sampling clock CK, a header generation circuit 102 for generating an MPEG2-TS packet header, and a synchronous timing detection circuit 103 for detecting a horizontal synchronizing signal for the video data VD. The format conversion circuit 100 also includes a counter 104 which counts the number of bytes of packet header and the number of bytes of video data VD, and a switch 105 which selects the packet header until the counted number of bytes reaches four bytes, and then selects the video data read out of the FIFO memory 101.
Claims7
A format conversion circuit comprising:
- a memory for storing video data;
- header generation device for generating a packet header that adheres to a standard for motion picture compression;
- synchronous timing detector for detecting a synchronizing signal for the video data;
- and
- selection device for repeating the selection of the packet header generated by said header generation device and the selection of a predetermined amount of video data read out of said memory as a payload responsive to the packet header, during an interval from when said synchronous timing detection device detects the synchronizing signal until it detects the next synchronizing signal.
A format conversion circuit for converting the format of video data to a pseudo MPEG2-TS format, comprising:
- a FIFO memory for storing the video data in response to a clock for the video data;
- a header generation circuit for generating an MPEG2-TS packet header in response to the clock for the video data;
- a synchronous timing detection circuit for detecting a horizontal synchronizing signal for the video data;
- a counter, reset in response to the horizontal synchronizing signal detected by said synchronous timing detection circuit, for counting the number of bytes of packet header output from said header generation circuit and the number of bytes of video data read out of said FIFO memory;
- and
- a switch, which selects the packet header generated by said header generation circuit until the number of bytes counted by said counter reaches the number of bytes of packet header as specified by MPEG2-TS, and selects the video data read out of said FIFO memory after the number of bytes counted by said counter has reached the number of bytes of packet header as specified by MPEG2-TS.
A method for converting the format of data, said method comprising:
- storing video data;
- generating a packet header that adheres to a standard for motion picture compression;
- detecting a synchronization signal for the video data;
- and
- repeating the generation of a packet header and selecting a predetermined amount of the video data as a payload responsive to latter said packet header, during an interval between the detection of at least two of the synchronization signals.
A program storage device readable by a digital processing apparatus and having a program of instructions which are tangibly embodied on the storage device and which are executable by the processing apparatus to peform a method of converting the format of data, said method comprising:
- storing video data;
- generating a packet header that adheres to a standard for motion picture compression;
- detecting a synchronization signals for the video data;
- and
- repeating the generation of a packet header and selecting a predetermined amount of the video data as a payload responsive to latter said packet header, during an interval between the detection of at least two of the synchronization signals.
Dependencies are inferred from the claim text.