Adaptive clock-less equalizer circuit
AssigneePlexus Networks, Inc.
InventorRamin Shirani
Life of this patent
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Abstract
A method and system for adaptive equalization without having to have a phase locked loop to recover the data bits is disclosed. This provides a clock-less equalization method. The algorithm also does not necessitate the digitization of all tap values, as is typically the case for DSP based equalizers. A system and method in accordance with the present invention can be utilized advantageously in devices where binary data is traveling through fiber (both single mode and multi-mode fiber) contaminated by certain characteristics of the fiber, which cause impairments. For a given data frequency, this impairments limit the length of the fiber that can be used for transmission of the data, and thus require equalization.
Claims2
A circuit for equalizing a signal comprising;
- feed-forward equalizer (FFE) for receiving an input signal providing a partially equalized signal;
- a slicer for receiving the partially equalized signal for providing decoded bit values for the partially equalized signal;
- a signal quality circuit for measuring the error in the signal from the FFE and providing an error output;
- and
- a convergence algorithm circuit for receiving the error output and controlling the FFE and the DFE, wherein an optimum equalized signal is provided and the recovered clock signal is independent of the equalization.
Dependencies are inferred from the claim text.