Apparatus for multiplexing signals through I/O pins

An apparatus that selectively multiplexes a plurality of signal lines through an I/O pin on a semiconductor chip, wherein the semiconductor chip is a core logic chip that couples together a processor, a memory and a peripheral bus in a computer system, the apparatus comprising:

• the semiconductor chip;
• the I/O pin on the semiconductor chip, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip;
• a transmitting circuit that is configured to selectively multiplex the plurality of signal lines onto the I/O pin;
• a receiving circuit that is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so the multiplexed data is separated into distinct signals in the receiving circuit;
• wherein the transmitting circuit and the receiving circuit are driven by a common clock signal coupled to both the transmitting circuit and the receiving circuit;
• an initialization circuit, coupled to the transmitting circuit and the receiving circuit, that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one selected signal line from the plurality of signal lines through the I/O pin;
• wherein the initialization circuit communicates information identifying the at least one selected signal line to both the transmitting circuit and the receiving circuit;
• wherein the initialization circuit is configured to initialize the transmitting circuit and the receiving circuit during a computer system boot up operation;
• and
• a synchronizing circuit, coupled to the transmitting circuit and the receiving circuit, that synchronizes the transmitting circuit and the receiving circuit by simultaneously sending a reset signal to both the transmitting circuit and the receiving circuit.

An computer system that selectively multiplexes a plurality of signal lines through an I/O pin, comprising:

• a processor;
• a memory;
• a semiconductor chip within the computer system containing circuitry for performing computer system operations;
• the I/O pin on the semiconductor chip, for coupling a signal line within the semiconductor chip to a signal line outside of the semiconductor chip;
• a transmitting circuit that is configured to selectively multiplex the plurality of signal lines onto the I/O pin;
• a receiving circuit that is configured to receive multiplexed data from the I/O pin, and to reverse the multiplexing so that values originally from the multiplexed signal lines are separated into distinct signals in the receiving circuit;
• wherein the transmitting circuit and the receiving circuit are driven by a common clock signal coupled to both the transmitting circuit and the receiving circuit;
• and
• an initialization circuit, coupled to the transmitting circuit and the receiving circuit, that selectively configures the transmitting circuit and the receiving circuit to multiplex at least one of the plurality of signal lines through the I/O pin.