US 2004/0165611 A1Published application

Area efficient serializer implementation for small functional-to-serial clock ratios

AssigneeTexas Instruments Incorporated

InventorsSubash Chandar Govindarajan, Sanjay Shinde

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Abstract

This invention adds one extra bit which can be viewed as a shadow of most significant bit of the serial register. This extra register bit is referred as buffer_flop. When the receive data is coming in, the data bits keep shifting into the serial register of the serializer block bit by bit. The first bits enters into the most significant bit of the serial register and is shifted towards the least significant bit of the serial register. When a whole block of bits (32 bits) are received, the serializer is full and is read into the VBUS clock domain. The first bit of next block of bits is stored in the buffer flop. The second bit is stored in the most significant bit of the serializer and the buffer flop bit is copied into the second most significant bit of the serializer. Subsequent bits are received and right shifted by one.

A data serializer comprising:

a input terminal receiving serial bits of data in data blocks of N bits;
a buffer-flip-flop having an input connected to input terminal and an output for storing a bit received at said input;
a most significant bit flip-flop having an input connected to said input terminal, an output and a hold terminal for storing a bit received at said input;
a multiplexer having a first input connected to said output of said buffer-flip-flop, a second input connected to said output of said most significant bit flip-flop, a control input and an output, said multiplexer selectively outputting one of said first input or said second input corresponding to a control signal at said control input;
a serial chain of N−1 bit flip-flops, each bit flip-flop having a input connected to an output of a prior bit flip-flop in said serial chain for storing a bit received at said input, a first bit flip-flop of said serial chain having an input connected to said output of said multiplexer;
a multibit register having a N parallel bit inputs, a most significant bit input connected to said output of said most significant bit flip-flop, N−1 less significant bit input connected to respective outputs of said serial chain of N−1 bit flip-flops, and a load enable input, said multibit register stores bits at said input upon a load enable signal at said load enable input;
a control circuit connected to said input terminal, said most significant bit flip-flop, multiplexer having a first input connected to said output of said buffer-flip-flop, a second input connected to said output of said most significant bit flip-flop, a control input and an output, said multiplexer, said serial chain of N−1 bit flip-flops and said multibit register, said control circuit
on a first bit of a data block, holding data in said most significant bit register and said serial chain of N−1 bit flip-flops,
on a second bit of a data block, supplying a control signal to said multiplexer to select said first input and transferring data from each bit flip-flop of said serial chain of N−1 bit flip-flops to a next bit flip-flop in said serial chain,
on bits of a data block other than a first, second or last bit, supplying a control signal to said multiplexer to select said second input and transferring data from each bit flip-flop of said serial chain of N−1 bit flip-flops to a next bit flip-flop in said serial chain,
on a final bit of a data block supplying a load enable signal to said load enable input of said multibit register.

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Abstract

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