Decoder having analog PLL circuit and digital PLL circuit
OwnerHideki Hirayamainventor
Life of this patent
Estimating the term…
Abstract
A decoder for improving efficiency of demodulation of address information, which is recorded by performing phase-modulation on the wobble of a groove. The decoder demodulates the address information based on the phase inversion pattern of an ADIP, which is detected using a first clock signal generated by a digital PLL circuit, until an analog PLL circuit is locked. The decoder demodulates the address information based on the phase inversion pattern of the detected ADIP using a second clock signal, which is generated by the analog PLL circuit, after the analog PLL circuit is locked.
Claims8
A decoder for demodulating address information using a wobble signal, the decoder comprising:
- a digital PLL circuit for generating a first clock signal and synchronizing the first clock signal with the wobble signal based on a difference between the phase of the wobble signal and the phase of the first clock signal;
- an analog PLL circuit for generating a second clock signal and synchronizing the second clock signal with the wobble signal based on a difference between the phase of the wobble signal and the phase of the second clock signal;
- and
- a demodulator, connected to the digital PLL circuit and the analog PLL circuit, for sampling the wobble signal using either the first clock signal or the second clock signal to demodulate the address information.
A decoder for demodulating address information using a wobble signal, the decoder comprising:
- a digital PLL circuit for generating a first clock signal and synchronizing the first clock signal with the wobble signal based on a difference between the phase of the wobble signal and the phase of the first clock signal;
- an analog PLL circuit for generating a second clock signal and synchronizing the second clock signal with the wobble signal based on a difference between the phase of the wobble signal and the phase of the second clock signal;
- a detection circuit for comparing the wobble signal and the second clock signal, detecting whether the second clock signal is synchronized with the wobble signal, and generating an active select signal when the second clock signal is synchronized with the wobble signal;
- and
- a demodulator, connected to the digital PLL circuit, the analog PLL circuit, and the detection circuit, for sampling the wobble signal using the first clock signal to demodulate the address information when the select signal is inactive and for sampling the wobble signal using the second clock signal to demodulate the address information when the select signal is active.
Dependencies are inferred from the claim text.