Zero latency-zero bus turnaround synchronous flash memory

A method of reducing latency in a synchronous memory device comprising:

• receiving write data on a first clock cycle;
• storing the write data and executing a data write operation;
• and
• executing a data read operation on a next clock cycle immediately following the first clock cycle.

A method of operating a synchronous memory bus in a memory system, the method comprises:

• providing a read command across a synchronous memory bus to a synchronous memory device to initiate a read operation;
• providing a memory array address across the synchronous memory bus to the synchronous memory device on a first clock cycle of the synchronous memory bus to perform the read operation;
• and
• providing a first command of a write command sequence across the synchronous memory bus to the synchronous memory device on a second clock cycle immediately following the first clock cycle to initiate a write operation such that the write command is provided prior to or concurrently with providing output read data from the read operation on an external data connection of the synchronous memory device.

A method of operating a synchronous memory bus in a memory system, the method comprises:

• providing a write command across a synchronous memory bus to a synchronous memory device to initiate a write operation;
• providing write data across a synchronous memory bus to the synchronous memory device on a first clock cycle of the synchronous memory bus;
• and
• providing a read command across the synchronous memory bus to the synchronous memory device on a second clock cycle immediately following the first clock cycle to initiate a read operation.