Pseudo-static synchronous semiconductor memory device
AssigneeRenesas Technology Corp.
InventorAkira Yamazaki
Life of this patent
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Abstract
For a pseudo-SRAM (Static Random Access Memory) macro operating in synchronization with a clock signal, a page operation instructing signal instructing a page operation and a page close instructing signal instructing completion of the page operation are prepared as control signals designating operation modes. A pseudo-SRAM can be selectively operated in a page mode in accordance with the page operation instructing signal and the page close instructing signal, and an operation of row-related circuitry in each clock cycle can be inhibited so that an average power consumption can be reduced. The power consumption of the pseudo-SRAM can be reduced without lowering an operation speed.
Claims10
A synchronous semiconductor memory device operating like a static memory, comprising:
- a plurality of dynamic memory cells arranged in rows and columns;
- signal input circuitry taking in an external operation control signal in synchronization with a basic clock signal, and producing an internal operation instructing signal;
- row select circuitry for selecting, when activated, a row of the memory cells in accordance with an external row address signal;
- column-related circuitry for selecting, when activated, a column of the memory cells in accordance with an external column address signal, and performing data access to a selected column;
- and
- control circuitry operating for activating and deactivating sequentially said row select circuitry and said column-related circuitry in a predetermined sequence in accordance with a first internal operation instructing signal provided from said signal-input circuitry, for inhibiting deactivation of said row select circuitry to maintain said row select circuitry in an active state in accordance with a second internal operation instructing signal provided from said signal input circuitry, and for deactivating said row select circuitry maintained in the active state in accordance with a third internal operation instructing signal provided from said signal input circuitry.
Dependencies are inferred from the claim text.