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US 2004/0165468 A1Published application
User selectable banks for dram
AssigneeMicron Technology, Inc.
InventorChristopher S. Johnson
Life of this patent
Estimating the term…
Abstract
A memory device includes a configurable array of memory cells. A number of array banks is configured based upon data stored in a mode register or decoded by logic circuitry. The memory device remains a full capacity memory, regardless of the number of array banks. Memory address decoding circuitry is adjusted to route address signals to or from a bank address decoder based upon the number of array banks selected.
Claims44
A system, comprising:
- a controller;
- and
- a memory device coupled to the controller to receive signals therefrom, and comprising:
- an array of memory cells arranged in a plurality of addressable banks, each bank comprises addressable rows and columns of memory cells;
- a mode register;
- and
- address circuitry coupled to the mode register to configure the addressable banks in response to a program state of the mode register.
4 more elements
A system, comprising:
- a controller;
- and
- a dynamic random access memory device coupled to the controller and comprising:
- an array of X memory cells;
- a mode register;
- and
- address circuitry coupled to the mode register to configure the array in response to a program state of the mode register, wherein the mode register defines a number of addressable banks of the array.
4 more elements
A system, comprising:
- a controller;
- and
- a synchronous dynamic random access memory (SDRAM) coupled to the controller and comprising:
- an array of X memory cells;
- a mode register;
- a column address decoder;
- a row address decoder;
- a bank address decoder;
- and
- address signal circuitry coupled to a plurality of address signal input connections, the address signal circuitry routes a selected one of the plurality of address input connections to either the row or bank address decoder in response to data stored in the mode register.
7 more elements
A system, comprising:
- a controller;
- and
- a synchronous dynamic random access memory (SDRAM) coupled to the controller and comprising:
- an array of X memory cells;
- at least one external input connection to receive a configuration signal;
- logic circuitry coupled to the at least one external input connection;
- a column address decoder;
- a row address decoder;
- a bank address decoder;
- and
- address signal circuitry coupled to a plurality of address signal input connections, the address signal circuitry routes a selected one of the plurality of address input connections to either the row or bank address decoder in response to the logic circuitry.
8 more elements
A system, comprising:
- a controller;
- and
- a memory device coupled to the controller to receive signals including an input signal therefrom, and comprising:
- an array of memory cells arranged in a plurality of addressable banks, each bank comprises addressable rows and columns of memory cells;
- a decode circuit to decode the input signal;
- and
- address circuitry coupled to the decode circuit to configure the addressable banks in response to a program state of the input signal.
4 more elements
A system, comprising:
- a controller providing an input signal;
- and
- a dynamic random access memory device coupled to the controller and comprising:
- an array of X memory cells;
- a decode circuit to decode the input signal;
- and
- address circuitry coupled to the decode circuit to configure the array in response to a program state of the input signal, wherein the input signal defines a number of addressable banks of the array.
4 more elements
A memory device, comprising:
- an array of memory cells arranged in a plurality of addressable banks, each bank comprises addressable rows and columns of memory cells;
- a decode circuit to decode an external input signal;
- and
- address circuitry coupled to the decode circuit to configure the addressable banks in response to a program state of the external input signal.
1 more element
A dynamic random access memory comprising:
- an array of X memory cells;
- a decode circuit to decode an external input signal;
- and
- address circuitry coupled to the decode circuit to configure the array in response to a program state of the external input signal, wherein the mode register defines a number of addressable banks of the array.
1 more element
A synchronous dynamic random access memory (SDRAM) comprising:
- an array of X memory cells;
- a decode circuit to decode an external input signal;
- a column address decoder;
- a row address decoder;
- a bank address decoder;
- and
- address signal circuitry coupled to a plurality of address signal input connections, the address signal circuitry routes a selected one of the plurality of address input connections to either the row or bank address decoder in response to data decoded by the decode circuit.
4 more elements
A method of operating a memory device comprising:
- receiving an external input signal at decode circuitry of the memory device;
- and
- adjusting address circuitry of the memory device in response to the decoded external input signal, wherein the address circuitry configures a number of addressable banks of a memory cell array.
A method of operating a memory system comprising:
- outputting decode circuitry data from a processor to a memory device, wherein the decode circuitry decodes an external input signal to generate bank count data;
- and
- adjusting address circuitry of the memory device in response to the decoded external input signal, wherein the address circuitry configures a number of addressable banks of a memory cell array using the bank count data.
Dependencies are inferred from the claim text.