Fast sensing scheme for floating-gate memory cells

A flash memory device, comprising:

• a global bit line;
• a sensing device for sensing a programmed state of a target memory cell, wherein the sensing device includes an input node selectively coupled to the global bit line and wherein the sensing device includes a first precharging path coupled to the input node for precharging the input node and the global bit line during a sensing operation;
• and
• a second precharging path coupled to the global bit line for precharging the input node and the global bit line during the sensing operation.

A flash memory device, comprising:

• an array of flash memory cells;
• a plurality of sensing devices each having an input node and a first precharging path coupled to the input node, wherein each input node is selectively coupled to one of a plurality of global bit lines, wherein each global bit line is selectively coupled to one of a plurality of local bit lines, and wherein each local bit line is coupled to at least one of the flash memory cells;
• and
• a plurality of second precharging paths each coupled to one of the global bit lines in a one-to-one relationship;
• wherein each of the first precharging paths is coupled to selectively apply a first precharge potential to its associated input node;
• and
• wherein each of the second precharging paths is coupled to selectively apply a second precharge potential to its associated global bit line.

A flash memory device, comprising:

• a global bit line coupled to a local bit line through a first pass circuit, the local bit line coupled to a target memory cell of the flash memory device;
• a sensing device for sensing a programmed state of the target memory cell, wherein the sensing device includes an input node selectively coupled to the global bit line through a second pass circuit and wherein the sensing device includes a p-channel field-effect transistor coupled between a first potential node and the input node;
• and
• a second precharging path coupled to the global bit line for precharging the input node and the global bit line during the sensing operation, the second precharging path comprising an n-channel field-effect transistor coupled between a second potential node and the second pass circuit.