Sense amplifying circuit and bit comparator with the sense amplifying circuit

A sense amplifying circuit comprising:

• a selecting unit for selecting one pair from a first pair of a first signal and a first inverted signal and a second pair of a second signal and a second inverted signal, in response to a first level of a clock signal, a selection signal, and an inverted selection signal;
• a sensing unit for sensing voltage levels of one pair of signals selected from the first and second pairs;
• a latching unit for precharging first and second nodes in response to a second level of the clock signal and controls voltage levels of the first and second nodes in response to a sensing result of the sensing unit;
• and
• an output unit for inverting the voltage levels of the first and second nodes to generate first and second output signals.

A bit comparator comprising:

• a random access memory cell for receiving and storing data and inverted data having an opposite level to the data from a pair of data lines to generate a selection signal and an inverted selection signal in response to a control signal;
• a selecting unit for selecting one pair from a first pair of first signal and first inverted signal and a second pair of second signal and second inverted signal in response to a first level of a clock signal, the selection signal, and the inverted selection signal;
• a sensing unit for sensing voltage levels of one pair of signals selected from the first and second pairs;
• a latching unit for precharging first and second nodes in response to a second level of the clock signal and controls voltage levels of the first and second nodes in response to a sensing result of the sensing unit;
• and
• an output unit for inverting the voltage levels of the first and second nodes to generate first and second output signals and determines in response to a level of the second output signal whether the data and the inverted data coincide with the first signal and the first inverted signal.