US 2004/0165456 A1 · Semiconductor memory having a defective memory cell relieving circuit

Abstract

In a semiconductor memory incorporating therein a circuit for relieving a defective memory cell, a memory cell array constituted of a number of main memory cells MC00 to MCij is added with one column of redundant memory cells MC0j+1 to MCij+1 and one word line of substitution information storing memory cells MCRA0 to MCRAj+1. In only a first cycle after the power supply is turned on, the substitution information DR0 to DRj is read out from the substitution information storing memory cells by use of a writing/reading circuit associated with the main memory cells, and is transferred to and held in a control circuit. In a second and succeeding cycles, the control circuit generates Y selection circuit control signals CS0 to CSj on the basis of the substitution information held in the control circuit, and a Y selection circuit is controlled by the control signals CS0 to CSj so as to selectively connect the columns other than a defective column to an input/output line. Thus, a chip area overhead attributable to the installation of the defective memory cell relief circuit is minimized. In addition, an address comparing circuit for a defective memory cell substitution is no longer necessary, and an access time overhead attributable to the address substitution operation does not occur.

Claims36

Dependent claims

A semiconductor memory including a memory cell array constituted of a number of memory cells arranged in the form of a matrix having a number of rows and a number of columns, and a defective memory cell relief means, wherein said memory cell array includes main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, and said defective memory cell relief means includes a means for operating, in place of a column including a defective memory cell, a non-defective column adjacent to said column including the defective memory cell.

A semiconductor memory comprising

a memory cell array including main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, said substitution information storing memory cells being constituted of a rewritable non-volatile memory cell;
a Y selection circuit associated with said memory cell array and receiving a Y selection signal to connect an input/output line to a bit line of the column designated by said Y selection signal;
a control circuit for generating a control signal, when substitution information read out from said substitution information storing memory cells before an ordinary reading/writing operation indicates that a column including a defective memory cell should be replaced with another column having no defective memory cell, said control signal being supplied to said Y selection circuit for inhibiting access to said column including the defective memory cell and for replacing said column including the defective memory cell by one column of the other columns and said at least one column of redundant memory cells,
said Y selection circuit being so configured that when the column designated by said Y selection signal is said column including the defective memory cell, said Y selection circuit selects a column adjacent to the column designated by said Y selection signal, and connects said input/output line to a bit line of the selected column adjacent to the column designated by said Y selection signal.

1 more element

A semiconductor memory comprising a memory cell array divided into a plurality of sub-arrays coupled through a local bus, each of said sub-arrays including a number of main memory cells arranged in the form of a matrix having a number of rows and a number of columns, at least one row of substitution information storing memory cells and at least one column of redundant memory cells, each of said sub-arrays being associated with a Y selection circuit and a plurality of sense amplifiers each provided for a bit line of one corresponding column,

wherein in the bit line of each column, a transfer gate is inserted between said substitution information storing memory cells and said main memory cells and said redundant memory cells, and is controlled by a separation control signal to separate said main memory cells and said redundant memory cells from the associated sense amplifiers and said substitution information storing memory cells,
wherein a pair of said sub-arrays are mated so that said substitution information storing memory cells in each of said pair of sub-arrays store substitution information for the other of said pair of sub-arrays, and when one of said pair of sub-arrays is read out, the substitution information for said one of said pair of sub-arrays is read out from said substitution information storing memory cells in the other of said pair of sub-arrays while separating said main memory cells and said redundant memory cells in the other of said pair of sub-arrays from the associated sense amplifiers and said substitution information storing memory cells in the other of said pair of sub-arrays by turning off said transfer gates in the other of said pair of sub-arrays, and the read-out substitution information is transferred through said local bus, as a control signal, to said Y selection circuit associated with said one of said pair of sub-arrays,
so that said Y selection circuit associated with said one of said pair of sub-arrays receives a Y selection signal and said control signal, to connect the bit line of the column designated by said Y selection signal to an input/output line when said control signal indicates that the column designated by said Y selection signal is not a column including a defective memory cell, and to connect said input/output line to a column adjacent to the column designated by said Y selection signal when said control signal indicates that the column designated by said Y selection signal is a column including a defective memory cell.

A semiconductor memory comprising:

a memory cell array including a number of main memory cells arranged in the form of a matrix having a number of rows and a number of columns and at least one column of redundant memory cells;
a plurality of sense amplifiers each provided for a bit line of one corresponding column in said memory cell array;
a Y selection circuit associated with said memory cell array;
a control circuit including a plurality of substitution information storing memory cells for generating, on the basis of substitution information read out from said substitution information storing memory cells, a control signal to said Y selection circuit for inhibiting access to a column including a defective memory cell and for replacing said column including the defective memory cell by one column of the other columns and said at least one column of redundant memory cells,
wherein when a power supply is turned on, said substitution information is read out from said substitution information storing memory cells, and said Y selection circuit receiving a Y selection signal and said control signal, connects the bit line of the column designated by said Y selection signal to an input/output line when said control signal indicates that the column designated by said Y selection signal is not a column including a defective memory cell, and to connect said input/output line to a column including no defective memory cell when said control signal indicates that the column designated by said Y selection signal is a column including a defective memory cell.

2 more elements

Dependencies are inferred from the claim text.

Semiconductor memory having a defective memory cell relieving circuit

Life of this patent

Semiconductor memory having a defective memory cell relieving circuit

Life of this patent

Abstract

Claims36