Semiconductor memory device including RAS guarantee circuit
AssigneeRenesas Technology Corp.
InventorMasaya Nakano
Life of this patent
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Abstract
An internal RAS generating circuit generates an internal signal instructing activation of a word line, based on a control command received from the outside. The internal RAS generating circuit activates the internal signal at least during a period in which an internal RAS guarantee signal received from an internal RAS guarantee signal generating circuit is asserted, regardless of the control command instructing inactivation of the word line. In a normal operation mode, the internal RAS guarantee signal generating circuit activates the internal RAS guarantee signal until a prescribed period guaranteeing a restoring operation elapses, while in the test mode, it inactivates the internal RAS guarantee signal.
Claims6
A semiconductor memory device continuing an access operation to a memory cell storing data at least until a prescribed period elapses, upon receiving a first control command to start access to said memory cell in a normal operation mode, comprising:
- a word line and a bit line pair connected to said memory cell;
- and
- a control circuit controlling said access operation based on a control command received from outside;
- wherein
- said prescribed period is a period in which restoration of said data to said memory cell is completed,
- said control circuit terminates control of said access operation in response to a second control command received from the outside regardless of elapse of said prescribed period, upon receiving said first control command in a test mode.
Dependencies are inferred from the claim text.