Semiconductor memory device
AssigneeSeiko Instruments Inc.
InventorHiroki Wake
Life of this patent
Estimating the term…
Abstract
To provide a semiconductor memory device that suppresses a terminal leak current in a test operation mode. The present invention has the following feature. For suppressing the terminal leak current in the operation mode, a layout is adopted in which a polysilicon layer overlaps with an end of a drain, the layer forming a gate electrode of a protective transistor for protecting an IC when being subjected to an electrostatic noise, the protective transistor being connected to an external terminal for the test operation mode. Consequently, a breakdown voltage of an electrostatic breakdown voltage protective transistor is increased.
Claims2
A semiconductor memory device comprising:
- an external terminal to which a voltage for switching an operation mode is applied;
- a protective transistor connected between the external terminal and a ground;
- and
- a voltage detection circuit for detecting a voltage of the external terminal and outputting a signal for switching a first operation mode to a second operation mode when the detected voltage is a predetermined voltage or higher,
- wherein the protective transistor has a drain region surrounded by a gate electrode.
Dependencies are inferred from the claim text.