Method and architecture to calibrate read operations in synchronous flash memory
AssigneeMicron Technology, Inc.
InventorFrankie F. Roohparvar
Life of this patent
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Abstract
Architecture to calibrate read operations in non-volatile memory devices. In one embodiment, a synchronous flash memory is disclosed. The synchronous flash memory includes a read sense amplifier, a verification sense amplifier, a switch, and an output buffer. The switch alternates electrical connection of the output buffer with the read sense amplifier and the verification sense amplifier. By measuring the distributions of voltage thresholds of erased cells versus voltage thresholds of programmed cells, differences in offsets between read state and write state of memory cells are determined. A specific margin is determined to ensure proper reads of the memory cells.
Claims21
A method of calibrating a non-volatile memory comprising:
- reading a data state of a plurality of memory cells with a first sense amplifier;
- reading the data state of the plurality of memory cells with a second sense amplifier;
- comparing outputs of the first and second sense amplifiers to determine offsets between the first and second sense amplifiers;
- and
- adjusting either the first or second sense amplifier to calibrate the first and second sense amplifiers.
A method of calibrating a non-volatile memory comprising:
- storing a test pattern in the non-volatile memory;
- reading the test pattern with a first read circuit;
- reading the test pattern with a second read circuit;
- outputting the read test pattern from the first and second read circuit to an external connection;
- determining if an offset exists between the first and second read circuits;
- and
- adjusting either the first or second read circuit if an offset is determined.
A system comprising:
- a memory test circuit;
- and
- a non-volatile memory coupled to the memory test circuit comprising,
- an array of memory cells,
- a first read path having a first read circuit,
- a second read path having a second read circuit, and
- switch circuitry, wherein the switch circuitry is adapted to select the first or second read circuits and couple to the memory test circuit via external data connections.
A non-volatile memory comprising:
- an array of memory cells;
- a first read path having a first read circuit;
- a second read path having a second read circuit;
- and
- switch circuitry to select the first or second read circuits and couple to external data connections.
Dependencies are inferred from the claim text.