Flash memory cell arrays having dual control gates per memory cell charge storage element

In a non-volatile memory including an array of charge storage elements positioned across a substrate surface, a method of coupling voltages to designated ones of the storage elements for simultaneously programming or reading their charge storage states representative of data stored thereby, comprising applying different voltages to a plurality of control gates having lengths extending across the array between charge storage elements that are capacitively coupled with a pair of the plurality of control gates on either side thereof, including placing first voltage levels on those of the plurality of control gates adjacent the designated storage elements and second voltage levels on those of the plurality of control gates not adjacent to the designated storage elements, wherein, the first and second voltages are significantly different.

A non-volatile memory for programming and reading data, comprising:

• an array of charge storage elements positioned across a semiconductor substrate,
• a plurality of control gate lines extending across the array in a manner that opposing sidewalls of individual charge storage elements are capacitively coupled with at least two of the control gate lines, and
• a decoder and voltage supply connected to the control gate lines to couple controlled voltages to the charge storage elements capacitively coupled therewith during programming data thereto and reading data therefrom.

A non-volatile memory cell array comprising a plurality of strings of series connected memory cells extending in a first direction across a semiconductor substrate, the memory cells including charge storage elements, the array including control lines extending in a second direction across the strings of memory cells and including control gates adjacent charge storage elements thereof, the first and second directions being orthogonal with each other, wherein the control gates are positioned between adjacent storage elements of the memory strings in a manner to be capacitively coupled with sidewalls of the adjacent storage elements of the memory cell strings on opposite sides of the control gates.

A method of making a memory cell array on a semiconductor substrate, comprising:

• forming a rectangular array of columns and rows of floating gates across a surface area of the substrate with a first layer of dielectric therebetween, providing isolation of the floating gates across the substrate between columns thereof, and
• forming control gates extending across the substrate area perpendicular to said columns between rows of the floating gates in a manner that opposing sidewalls of the floating gates are capacitively coupled with walls of the control gates on opposite sides thereof through a second layer of dielectric and bottom surfaces of the control gates are capacitively coupled with the surface of the substrate over the well through a third layer of dielectric.

A method of operating a memory array on a semiconductor substrate, wherein strings of a plurality of more than two non-volatile memory transistors are connectable in series to designated bit lines, comprising utilizing potentials on conductive gate elements positioned in capacitive coupling with the substrate in regions between the memory transistors to selectively provide a level of conductivity in the substrate along the strings through such regions.