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US 2004/0165433 A1Published application
Flash memory with RDRAM interface
AssigneeMicron Technology, Inc.
InventorsFrankie Fariborz Roohparvar, Kevin C. Widmer
Life of this patent
Estimating the term…
Abstract
A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.
Claims21
A flash memory device comprising:
- an array of non-volatile memory cells;
- a clock signal connection to receive a clock signal comprising clock cycles;
- a rambus dynamic random access memory (RDRAM) interconnect configuration coupled to the array of non-volatile memory cells, the interconnect configuration comprising a multiplexed row address bus, a multiplexed column address bus, and data connections;
- and
- command logic coupled to the array to provide two data access operations per clock cycle.
2 more elements
The flash memory of claim 7 wherein the pre-charge circuitry pre-charges an active digit line that is coupled to a read memory cell to a voltage that is greater than a complementary digit line.
A processing system comprising:
- a processor;
- and
- a rambus dynamic random access memory compatible flash memory device coupled to the processor, the memory device comprising:
- an array of non-volatile memory cells;
- a clock signal connection to receive a clock signal comprising clock cycles;
- a rambus dynamic random access memory interconnect configuration coupled to the array of non-volatile memory cells, the interconnect configuration comprising a multiplexed row address bus, a multiplexed column address bus, and data connections that are burst oriented;
- and
- command logic coupled to the array to provide two data access operations per clock cycle starting at a selected location and continuing for a programmed number of locations in a programmed sequence.
5 more elements
A processing system comprising:
- a processor;
- a single communication bus coupled to the processor;
- a volatile memory device coupled to the single communication bus;
- and
- a rambus dynamic random access memory (RDRAM) compatible flash memory device coupled to the single communication bus, the memory device comprising:
- an array of non-volatile memory cells;
- a clock signal connection to receive a clock signal comprising clock cycles;
- and
- command logic coupled to the array to provide two data access operations per clock cycle following an RDRAM compatible format and starting at a selected location and continuing for a programmed number of locations in a programmed sequence.
6 more elements
Dependencies are inferred from the claim text.