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US 2004/0165432 A1Published application
Flash memory with RDRAM interface
AssigneeMicron Technology, Inc.
InventorsFrankie Friborz Roohparar, Kevin C. Widmer
Life of this patent
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Abstract
A flash memory has been described that has an interface corresponding to a rambus dynamic random access memory (RDRAM). The memory samples commands and addresses on a rising edge of a clock signal. The read and write data are provided on both the rising edge and the falling edge of the clock signal.
Claims20
A non-volatile memory device comprising:
- an array of non-volatile memory cells, wherein the array comprises bit lines coupled to the non-volatile memory cells;
- sense amplifier circuitry coupled to the bit lines, wherein the sense amplifier circuitry detects a differential voltage between the bit lines;
- a clock signal connection to receive a clock signal;
- a rambus dynamic random access memory (RDRAM) interconnect configuration coupled to the array of non-volatile memory cells, the interconnect configuration comprising a multiplexed row address bus, a multiplexed column address bus, and data connections;
- and
- output circuitry to provide output data on the data connections on rising and falling edges of the clock signal.
3 more elements
A flash memory device comprising:
- an array of non-volatile memory cells, wherein the array comprises bit lines coupled to the non-volatile memory cells;
- sense amplifier circuitry coupled to the bit lines, wherein the sense amplifier circuitry detects a differential voltage between the bit lines;
- pre-charge circuitry coupled to pre-charge the bit lines to first and second voltage levels to provide an initial differential voltage prior to sensing a memory cell;
- a clock signal connection to receive a clock signal;
- a rambus dynamic random access memory (RDRAM) interconnect configuration coupled to the array of non-volatile memory cells, the interconnect configuration comprising a multiplexed row address bus, a multiplexed column address bus, and data connections that are burst oriented;
- and
- output circuitry to provide output data on the data connections on rising and falling edges of the clock signal, the output circuitry is further adapted to provide the output data starting at a selected location and continuing for a programmed number of locations in a programmed sequence.
4 more elements
A processing system comprising:
- a processor;
- and
- a rambus dynamic random access memory (RDRAM) compatible non-volatile memory device coupled to the processor comprising:
- an array of non-volatile memory cells, wherein the array comprises bit lines coupled to the non-volatile memory cells;
- sense amplifier circuitry coupled to the bit lines, wherein the sense amplifier circuitry detects a differential voltage between the bit lines;
- a clock signal connection to receive a clock signal;
- an RDRAM interconnect configuration coupled to the array of non-volatile memory cells, the interconnect configuration comprising a multiplexed row address bus, a multiplexed column address bus, and data connections that are burst oriented;
- and
- output circuitry to provide output data on the data connections on rising and falling edges of the clock signal, the output circuitry is further adapted to provide the output data starting at a selected location and continuing for a programmed number of locations in a programmed sequence.
6 more elements
Dependencies are inferred from the claim text.