Integrated circuit devices having multiple precharge circuits and methods of operating the same

An integrated circuit device comprising:

• a pair of differential I/O lines;
• a driver circuit configured to operate responsive to a write command signal and to drive the pair of differential I/O lines;
• a first precharge circuit configured to precharge the pair of differential I/O lines to a first voltage during a first mode of operation responsive to an active command signal;
• a second precharge circuit configured to precharge the pair of differential I/O lines to a second voltage, lower than the first voltage, during a second mode of operation responsive to the active command signal;
• and
• a third precharge circuit configured to precharge the pair of differential I/O lines to a third voltage during a third mode of operation responsive to a data masking signal.

An integrated circuit memory device comprising:

• first and second memory banks comprising a first plurality of memory blocks and a second plurality of memory blocks, respectively;
• a first pair of differential I/O lines coupled to the first memory bank;
• a second pair of differential I/O lines coupled to the second memory bank;
• a first precharge circuit associated with the first memory bank;
• a second precharge circuit associated with the second memory bank, the first and second precharge circuits being configured to precharge the first pair of differential I/O lines and the second pair of differential I/O lines to a first voltage, respectively;
• a third precharge circuit associated with the first memory bank;
• a fourth precharge circuit associated with the third memory bank, the third and fourth memory banks being configured to precharge the first pair of differential I/O lines and the second pair of differential I/O lines to a second voltage, lower than the first voltage, respectively;
• and
• a timing control circuit configured to deactivate the first and second precharge circuits and activate the third and fourth precharge circuits responsive to assertion of an active command signal.

A method of operating an integrated circuit device comprising:

• driving a pair of differential I/O lines responsive to a write command signal;
• precharging the pair of differential I/O lines to a first voltage during a first mode of operation responsive to an active command signal;
• and
• precharging the pair of differential I/O lines to a second voltage, lower than the first voltage, during a second mode of operation responsive to assertion of the active command signal.

A method of operating an integrated circuit device comprising:

• driving a pair of differential I/O lines responsive to a write command signal;
• precharging the pair of differential I/O lines to a first voltage during a first mode of operation responsive to an active command signal;
• precharging the pair of differential I/O lines to a second voltage, lower than the first voltage, during a second mode of operation responsive to the active command signal;
• and
• precharging the pair of differential I/O lines to a third voltage during a third mode of operation responsive to a data masking signal.

A method of operating an integrated circuit device including a memory bank having a plurality of memory blocks and pairs of differential I/O lines coupled to the plurality of memory banks, the method comprising:

• precharging the pairs of differential I/O lines to a first voltage responsive to activation of an active command signal;
• pausing the precharging operation of the pair of differential I/O lines responsive to the activation of a write command signal;
• driving the pair of differential I/O lines according to external data;
• and
• precharging the pair of differential I/O lines to a second voltage, lower than the first voltage, responsive to assertion of the active command signal.