Semiconductor memory device
AssigneeKabushiki Kaisha Toshiba
InventorKeiichi Kushida
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Abstract
A semiconductor memory device includes first and second CMOS (complementary metal oxide semiconductor) inverter circuits each having a latch structure and a control transistor which is connected between a storage node of the first CMOS inverter circuit and a bit line and whose gate is connected to a word line. The device further includes a selection circuit to apply one of a first voltage and a second voltage different from the first voltage to a power supply node of at least the second CMOS inverter circuit. The selection circuit applies the second voltage to the power supply node of the second CMOS inverter circuit at least in “1” data write mode.
Claims16
A semiconductor memory device comprising:
- first and second CMOS (complementary metal oxide semiconductor) inverter circuits each having a latch structure;
- a control transistor which is connected between a storage node of the first CMOS inverter circuit and a bit line and whose gate is connected to a word line;
- and
- a selection circuit to apply one of a first voltage and a second voltage different from the first voltage to a power supply node of at least the second CMOS inverter circuit,
- wherein the selection circuit applies the second voltage to the power supply node of the second CMOS inverter circuit at least in “1” data write mode.
A semiconductor memory device having a memory structure in which a plurality of 5-transistor cells each including first and second CMOS (complementary metal oxide semiconductor) inverter circuits each having a latch structure and a control transistor which is connected between a storage node of the first CMOS inverter circuit and a bit line and whose gate is connected to a word line are connected in parallel to a plurality of bit lines and a plurality of word lines, the semiconductor memory device comprising:
- at least one VDD power line connected to a source terminal of a P-type MOS transistor of at least the second CMOS inverter circuit of each of the 5-transistor cells connected to the bit lines;
- and
- at least one selection circuit which applies a second voltage VDD−ΔV, which is lower than a first voltage VDD, to the source terminal of the P-type MOS transistor of the second CMOS inverter circuit of the 5-transistor cells through said at least one VDD power line at least in “1” data write mode.
A semiconductor memory device having a memory structure in which a plurality of 5-transistor cells each including first and second CMOS (complementary metal oxide semiconductor) inverter circuits each having a latch structure and a control transistor which is connected between a storage node of the first CMOS inverter circuit and a bit line and whose gate is connected to a word line are connected in parallel to a plurality of bit lines and a plurality of word lines, the semiconductor memory device comprising:
- at least one VSS power line connected to a source terminal of an N-type MOS transistor of at least the second CMOS inverter circuit of each of the 5-transistor cells connected to the bit lines;
- and
- at least one selection circuit which applies a second voltage VSS+ΔV, which is higher than a first voltage VSS, to the source terminal of the N-type MOS transistor of the second CMOS inverter circuit of the 5-transistor cells through said at least one VSS power line at least in “1” data write mode.
Dependencies are inferred from the claim text.