Ferroelectric write once read only memory for archival storage
AssigneeMicron Technology, Inc.
InventorLeonard Forbes
Life of this patent
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Abstract
Structures and methods for ferroelectric write once read only memory adapted to be programmed for long retention archival storage are provided. The write once read only memory cell includes a charge amplifier transistor. The transistor includes a source region, a drain region, and a channel region located between the source and the drain regions. A gate stack is located above the channel region. The gate stack includes; a gate oxide layer, a polysilicon interconnect on the gate oxide, a ferroelectric dielectric coupled to the polysilicon interconnect, and a control electrode coupled to the ferroelectric dielectric. A plug couples the source region to an array plate. A transmission line is coupled to the drain region.
Claims23
A memory array, comprising:
- an array plate;
- a number of memory cells, each cell including:
- a first source/drain region coupled to the array plate;
- a second source/drain region;
- a channel region between the first source/drain region and the second source/drain region;
- a dielectric layer located over the channel region;
- a gate electrode located over the dielectric layer;
- a ferroelectric dielectric coupled to the gate electrode;
- and
- a control electrode coupled to the ferroelectric dielectric.
A memory device, comprising:
- an array plate;
- a number of memory cells, each cell including:
- a first source/drain region coupled to the array plate;
- a second source/drain region;
- a channel region between the first source/drain region and the second source/drain region;
- a dielectric layer located over the channel region;
- a gate electrode located over the dielectric layer;
- a ferroelectric dielectric coupled to the gate electrode;
- a control electrode coupled to the ferroelectric dielectric;
- and
- a sense amplifier circuit coupled to the second source drain regions.
A memory array, comprising:
- an array plate;
- a number of memory cells, each cell including:
- a first source/drain region coupled to the array plate;
- a second source/drain region;
- a channel region between the first source/drain region and the second source/drain region;
- and
- a gate stack located over the channel region, wherein the gate stack includes two capacitors in series, wherein a first capacitor includes a semiconductor oxide dielectric and a second capacitor includes a ferroelectric dielectric.
A memory device, comprising:
- an array plate;
- a number of memory cells, each cell including:
- a first source/drain region coupled to the array plate;
- a second source/drain region;
- a channel region between the first source/drain region and the second source/drain region;
- and
- a gate stack located over the channel region, wherein the gate stack includes two capacitors in series, wherein a first capacitor includes a semiconductor oxide dielectric and a second capacitor includes a ferroelectric dielectric;
- and
- a sense amplifier circuit coupled to the second source drain regions.
A memory array, comprising:
- an array plate;
- a number of memory cells, each cell including:
- a first source/drain region coupled to the array plate;
- a second source/drain region;
- a channel region between the first source/drain region and the second source/drain region;
- a silicon oxide layer located over the channel region;
- a polysilicon layer located over the silicon oxide layer;
- a ferroelectric dielectric between a first platinum portion and a second platinum portion, wherein the first platinum portion is coupled to the polysilicon layer.
A memory array, comprising:
- an array plate;
- a number of memory cells, each cell including:
- a first source/drain region coupled to the array plate;
- a second source/drain region;
- a channel region between the first source/drain region and the second source/drain region;
- a dielectric layer located over the channel region;
- a gate electrode located over the dielectric layer;
- a dipole charge storing means coupled to the gate electrode;
- and
- a control electrode coupled to the dipole charge storing means.
Dependencies are inferred from the claim text.