US 2004/0165093 A1 · CMOS APS readout scheme that combines reset drain current and the source follower output

Abstract

A circuit and method for reducing noise in video imagers which takes advantage of the fact that the same image information is present in the drain current in a reset transistor used to reset a photodiode in a pixel as is present in the readout current. The noise is reduced by passing the multiplexed output voltage from the source follower output transistor in an APS imager system through a high pass filter to reduce the low frequency noise from the source follower. The drain current in the reset transistor used to reset the APS is passed through a low pass filter. The low pass filter output and the high pass filter output are then combined. Since the drain current in the reset transistor contains the same image information as the voltage output of the source follower output transistor the image information can be obtained by combining the output of the low pass filter and the output of the high pass filter. Since the low frequency noise components of the source follower output transistor have been suppressed combined outputs of the low pass filter and high pass filter will provide the image information with greatly suppressed low frequency noise.

Claims27

Dependent claims

A pixel circuit, comprising:

a photodiode having an anode;
a reset transistor, wherein said reset transistor is a field effect transistor having a drain connected to a first node and a source connected to said anode of said photodiode;
an output transistor, wherein said output transistor is a field effect transistor having a gate connected to said anode of said photodiode and a source;
a sample and hold circuit;
means for electrically connecting said source of said first output transistor to said sample and hold circuit or electrically isolating said source of said first output transistor from said sample and hold circuit;
a column select transistor, wherein said column select transistor is a field effect transistor having a drain connected to said sample and hold circuit, a gate connected to a column select input, and a source connected to a second node;
a first capacitor connected between said second node and an output node;
a resistor connected between said first node and said output node;
a second capacitor connected between said output node and ground potential.

6 more elements

A method of reading an active pixel sensor;

comprising:
providing a number of sensor circuits wherein each of said sensor circuits comprises a photodiode having an anode, a reset transistor having a source connected to said anode of said photodiode and a drain, an output transistor having a gate connected to said anode of said photodiode and a source, a sample and hold circuit, a row select transistor and a sample transistor connected in series between said source of said first output transistor and said sample and hold circuit, a column select transistor having a drain connected to said sample and hold circuit and a source;
providing a first node connected to a horizontal buss;
providing a second node connected to each of said drains of each of said reset transistors of each of said sensor circuits;
providing a filter capacitor connected between said first node and each of said sources of each of said column select transistors of each of said sensor circuits;
providing an output capacitor connected between said first node and ground potential;
turning off said reset transistor said sample transistor, and accumulating charge on each of said photodiodes in each of said sensor circuits during a charge integration period;
turning off said reset transistors, turning on said sample transistors, turning on said row select transistors and storing a signal at each of said sample and hold circuits in each of said sensor circuits after said charge integration period has been completed, wherein said signal stored at said sample and hold circuit in each of said sensor circuits is related to the potential of said anode of said photodiode in that said sensor circuit after said charge integration period has been completed;
and
turning on said reset transistors, turning off said sample transistors, and sequentially turning on each of said column select transistors after storing said signal at each of said sample and hold circuits after storing said signal at each of said sample and hold circuits in each of said sensor circuits;
thereby causing a reset current to flow from said second node to each of said drains of each of said reset transistors, signal currents to flow from each of said sample ha hold circuits into said first node, and providing an output signal to said horizontal bus comprising low frequency components of said reset current mixed with high frequency components of said signal currents.

8 more elements

Dependencies are inferred from the claim text.

CMOS APS readout scheme that combines reset drain current and the source follower output

Life of this patent

CMOS APS readout scheme that combines reset drain current and the source follower output

Life of this patent

Abstract

Claims27