Buffer circuit and active matrix display using the same

A buffer circuit comprising:

• a first transistor coupled between a first power source for supplying a first voltage of a first level and an output end;
• a second transistor coupled between a second power source for supplying a second voltage of a second level and the output end, wherein capacitance is formed between the gate of the second transistor and the output end;
• and
• a driving circuit for the first and second transistors, comprising a third transistor coupled between the gate of the second transistor and the second power source, the third transistor having a gate for receiving a first signal having a first signal level,
• wherein the driving circuit turns on the first transistor and turns off the second transistor when the first signal level is substantially the first level, and
• wherein the driving circuit turns on the third transistor to charge the capacitance with voltage, floats the gate node of the second transistor so that the second transistor can bootstrap, and turns off the first transistor, when the first signal level is substantially the second level.

An active matrix display comprising:

• a plurality of buffer circuits, each of the plurality of buffer circuits comprising:
• a first transistor coupled between a first power source for supplying a first voltage of a first level and a first node, the first transistor having a gate for receiving a first signal having a first signal level;
• a second transistor coupled between the first node and a second power source for supplying a second voltage of a second level, the second transistor having a gate for receiving a second signal having a second signal level, which is an inverse of the first signal level;
• a third transistor having a gate coupled to the first node, the third transistor being coupled between the first power source and a second node;
• a fourth transistor coupled between the second node and the second power source, the fourth transistor having a gate for receiving the first signal;
• a fifth transistor having a gate coupled to the second node, the fifth transistor being coupled between the first power source and an output end;
• and
• a sixth transistor having a gate coupled to the first node, the sixth transistor being coupled between the output end and the second power source, wherein capacitance is formed between the gate of the sixth transistor and the output end;
• a driving signal supply for supplying a plurality of first driving signals as the second signals to the plurality of buffer circuits, respectively;
• and
• a display panel including:
• a plurality of first signal lines for transmitting the first driving signals that are passed and output, respectively, through the buffer circuits;
• a plurality of second signal lines for respectively transmitting a plurality of second driving signals, the second signal lines being formed crossing the first signal lines;
• and pixel circuits coupled to the first and second signal lines, the pixel circuits being operable by the first and second driving signals.

An active matrix display comprising:

• a plurality of buffer circuits, each of the plurality of buffer circuits comprising:
• a first transistor coupled between a first power source for supplying a first voltage of a first level and an output end;
• a second transistor coupled between a second power source for supplying a second voltage of a second level and the output end, wherein capacitance is formed between the gate of the second transistor and the output end;
• and
• a driving circuit for the first and second transistors, comprising a third transistor coupled between the gate of the second transistor and the second power source, the third transistor having a gate for receiving a first signal having a first signal level,
• wherein the driving circuit turns on the first transistor and turns off the second transistor when the first signal level is substantially the first level, and
• wherein the driving circuit turns on the third transistor to charge the capacitance with voltage, floats the gate node of the second transistor so that the second transistor can bootstrap, and turns off the first transistor, when the first signal level is substantially the second level;
• a driving signal supply for supplying a plurality of first driving signals as the first signals to the plurality of buffer circuits, respectively;
• and
• a display panel including:
• a plurality of first signal lines for transmitting the first driving signals that are passed and output, respectively, through the buffer circuits;
• a plurality of second signal lines for respectively transmitting a plurality of second driving signals, the second signal lines being formed crossing the first signal lines;
• and pixel circuits coupled to the first and second signal lines, the pixel circuits being operable by the first and second driving signals.

A bootstrap circuit comprising:

• a first transistor coupled between a first power source for supplying a first voltage of a first level and an output end;
• a second transistor coupled between the output end and a second power source for supplying a second voltage of a second level, wherein capacitance is formed between a gate of the second transistor and the output end;
• and
• a driving circuit for receiving first and second signals having first and second signal levels, respectively, that are inverse of one another, and respectively turning on the first transistor and turning off the second transistor when the first signal level is substantially the first level, wherein
• the driver circuit applies a third voltage which has substantially the same voltage level as the second level to the gate of the second transistor to charge the capacitance with voltage, floats the gate node of the second transistor, and turns off the first transistor to bootstrap the second transistor, when the first signal level is changed to substantially the second level from substantially the first level.