PLL circuit and method of use
AssigneeLG Electronics Inc.
InventorJong-Hyuk Baek
Life of this patent
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Abstract
A PLL circuit may include a memory for storing a control voltage and a processor for loading a control voltage, which corresponds to a changed channel, from the memory when a system channel is changed, and providing the control voltage to a Voltage Control Oscillator (VCO). Whenever a system changes a channel, a control voltage of a pertinent channel frequency that has been stored in the memory may be used as an initial value of a control voltage provided to the VCO 50 so that a time (i.e., a lock time) to perform a phase lock looping may be remarkably reduced. This may improve a processing speed of various communication equipments and their performance.
Claims20
A phase lock loop (PLL) circuit comprising:
- a memory to store a control voltage;
- and
- a processor to load a control voltage, which corresponds to a changed channel, from the memory when a system channel is changed, and to provide the control voltage to a Voltage Control Oscillator (VCO).
A method for synchronizing a phase of a frequency in a PLL circuit comprising:
- storing a control voltage in a memory;
- loading the control voltage, which corresponds to a changed channel, from the memory to a VCO;
- and
- setting the control voltage as an initial control voltage.
A phase lock loop (PLL) circuit comprising:
- a voltage controlled oscillator (VCO) to output a signal based on a voltage of an input signal;
- a memory device to store a control voltage;
- and
- a processor to load the control voltage from the memory device to the VCO.
Dependencies are inferred from the claim text.