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US 2004/0164801 A1Published application
Methods and apparatus for amplification in high temperature environments
OwnerDonald Thomas McGrathinventor
Life of this patent
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Abstract
In one aspect, the present invention provides a method for amplifying a signal including generating an input signal and amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal.
Claims24
A method for amplifying a signal comprising:
- generating an input signal;
- and
- amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal.
A buffered field effect transistor logic (BFL) level-shifting/inverter circuit comprising:
- an input;
- an NMOS depletion mode inverter responsive to said inverter stage input to produce an inverted output;
- a buffered field effect transistor logic (BFL) stage comprising a first NMOS depletion mode field effect transistor (FET) having a first gate and an associated first channel, a second NMOS depletion mode FET having a second gate and an associated second channel, and a voltage drop circuit electrically connected in series between said first channel and said second channel;
- a first output at an electrical node between said voltage drop circuit and said first channel;
- and
- a second output at an electrical node between said voltage drop circuit and said second channel.
3 more elements
A buffered field effect transistor logic (BFL) level-shifting/inverter circuit comprising:
- an input;
- an NMOS depletion mode inverter responsive to said inverter stage input to produce an inverted output;
- a buffered field effect transistor logic (BFL) stage responsive to said inverted output, said BFL stage comprising a first NMOS depletion mode field effect transistor (FET) having a first gate and an associated first channel, a second NMOS depletion mode FET having a second gate and an associated second channel;
- and a resistor electrically connected in series between said first channel and said second channel;
- a first output at an electrical node between said resistor and said first channel;
- and
- a second output at an electrical node between said resistor and said second channel, wherein said circuit is fabricated on a silicon carbide substrate.
4 more elements
An operational amplifier circuit comprising:
- a first NMOS depletion mode amplification stage;
- a first NMOS depletion mode chopping switch responsive to a first chopping signal to chop an input signal to said first amplification stage;
- a second NMOS depletion mode chopping switch responsive to a level-shifted first chopping signal to chop an output signal from said first amplification stage;
- and
- an NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to a clock signal to generate said first chopping signal and said level shifted first chopping signal across a voltage dropping element.
2 more elements
An operational amplifier circuit comprising:
- a first NMOS depletion mode amplification stage;
- a first NMOS depletion mode chopping switch responsive to a first chopping signal to chop an input signal to said first amplification stage;
- a second NMOS depletion mode chopping switch responsive to a level-shifted first chopping signal to chop an output signal from said first amplification stage;
- and
- and an NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to a clock signal to generate said first chopping signal and said level shifted first chopping signal across a resistor;
- and further wherein said operational amplifier circuit is fabricated on a silicon carbide substrate.
3 more elements
An operational amplifier circuit comprising:
- a first NMOS depletion mode amplification stage having differential inputs and outputs;
- a first NMOS depletion mode chopping switch responsive to a first chopping signal and a second chopping signal to chop a differential input signal to said first amplification stage;
- a second NMOS depletion mode chopping switch responsive to a level-shifted first chopping signal and a level shifted second chopping signal to chop an output signal from said first amplification stage;
- a first NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to a clock signal to generate said first chopping signal and said level shifted first chopping signal across a first resistor;
- a second NMOS depletion mode buffered field effect transistor logic (BFL) level shifting/inverter circuit responsive to said clock signal to generate said second chopping signal and said level shifted second chopping signal across a second resistor;
- and
- a clock generator circuit configured to generate said clock signal.
4 more elements
A method for amplifying a signal comprising:
- generating an input signal;
- amplifying the input signal utilizing a chopper-stabilized, silicon carbide NMOS depletion mode operational amplifier to produce an amplified output signal;
- amplifying the input signal by chopping the input signal utilizing a first NMOS depletion mode chopping switch that is responsive to a first chopping signal to produce a first chopped input signal;
- and
- amplifying the first chopped input signal utilizing an NMOS depletion mode amplifier stage to produce an amplified chopped output signal.
2 more elements
Dependencies are inferred from the claim text.