Low power, area-efficient circuit to provide clock synchronization

A circuit for controllably asserting either an internal clock signal or an external clock signal on a clock signal bus of an integrated circuit comprising:

• an internal clock signal transport path that is operative, in the absence of said external clock signal being coupled to a prescribed conductor of said integrated circuit, to couple said internal clock signal as a default clock signal to said clock signal bus of said integrated circuit;
• and
• an external clock signal transport path that is operative, in response to said external clock signal being coupled to said prescribed conductor of said integrated circuit, to interrupt the coupling of said internal clock signal to said clock signal bus of said integrated circuit in and, in place thereof, to couple said external clock signal to said clock signal bus of said integrated circuit.

A clock signal generator that is exclusive of a clock selection pin comprising a multiplexer having a first input to which an external clock signal is applied and a second input to which an internal clock signal is applied, said external clock signal being further coupled to an inverting delay and to a first input of a logic circuit, the output of said inverting delay being coupled to a second input of said logic circuit, said logic circuit having an output thereof coupled to a control input of a switching device, said switching device having a current flow path coupled to a current source and in parallel with a capacitor, and wherein a common connection between said current source and said electrical energy storage device is coupled to a first input of a comparator, said comparator having a second input coupled to receive a reference voltage, and an output coupled to a select port of said multiplexer, and wherein said switching device is operative to repeatedly discharge the capacitor in accordance with said external clock signal, but to otherwise allow the capacitor to be charged by the current source, so that said external clock signal is coupled to the output of said multiplexer, as long as the capacitor is repeatedly discharged by said external clock signal at a frequency sufficient to maintain the voltage across said capacitor less than a prescribed reference voltage.