Non-volatile latch circuit and a driving method thereof

A method for driving a non-volatile latch circuit that comprises:

• a ferroelectric capacitor having a first electrode, a second electrode, and a ferroelectric film disposed between the first electrode and the second electrode;
• a first input terminal for applying a voltage to the first electrode;
• an inverter element having an input portion and an output portion, the input portion being connected to the second electrode of the ferroelectric capacitor;
• a second input terminal for applying a-voltage to the second electrode;
• a switching element connected between the second electrode and the second input terminal for switching the voltage applied to second electrode;
• and
• a third input terminal for applying a voltage to the switching element to change the on/off state thereof;
• the inverter element outputting a high-level voltage to the output portion when a low-level voltage, which is lower than the threshold of the inverter element, is applied to the input portion thereof, and outputting a low-level voltage to the output portion when a high-level voltage, which is higher than the threshold of the inverter element, is applied to the input portion thereof,
• the high-level voltage being applied to the first input terminal while the switching element is kept in the off state;
• and
• the voltage that is generated at second electrode by residual polarization in the ferroelectric film when a low-level voltage is sequentially applied being higher than the threshold voltage of the inverter element;
• the method for driving the non-volatile latch circuit also comprising a high-level latch step, a low-level latch step, and a reset step;
• the high-level latch step having a first write substep followed by a first read substep, wherein
• in the first write substep, a low-level voltage, which is lower than the threshold of the inverter element, is applied to the second input terminal, and a high-level voltage is applied to the third input terminal to turn on the switching element, so that the voltage applied to the input portion is made a low-level voltage that is lower than the threshold of the inverter element, and
• in the first read substep, the voltage that is applied to the input portion is kept at a level that is lower than the threshold of the inverter element;
• the low-level latch step having a second write substep followed by a second read substep, wherein
• in the second write substep, a high-level voltage is applied to the first input terminal to generate a high-level voltage that is higher than the threshold of the inverter element in the input portion, while the switching element is tuned off by applying a low-level voltage to the third input terminal, and
• in the second read substep, a high-level voltage, which is higher than the threshold of the inverter element, is kept in the input portion while the switching element is maintained in an off state;
• and
• in the reset step, a low-level voltage that is lower than the threshold of the inverter element is applied to the second input terminal, and the switching element is turned on.