Comparator
AssigneeKabushiki Kaisha Toshiba
InventorAkira Yasuda
Life of this patent
Estimating the term…
Abstract
A comparator compares a first binary input signal and a second binary input signal each binalized. A generator generates a reset signal at each rising edge or each falling edge of the first input signal. A counter counts the second input signal at each timing determined by the reset signal. The counted value represents a ratio of each frequency of the first input signal and the second input signal. A subtractor calculates a difference between the counted value and a set value representing a predetermined ratio of each frequency of the first input signal and the second input signal. An integrator integrates the difference. The integrated value represents a phase difference of the frequencies of the first input signal and the second input signal.
Claims12
A PLL circuit including a phase comparator to control an output signal of a variable frequency oscillator, a reference signal of a predetermined frequency is a first input signal, and one of an output signal and a divided signal of the output signal from the variable frequency oscillator is a second input signal,
- wherein the phase comparator for comparing the first input signal and the second input signal, comprising:
- a generator configured to generate a reset signal at each rising edge or each falling edge of the first input signal;
- a counter configured to count the second input signal at each interval determined by the reset signal, a counted value represents a ratio of frequencies of the first input signal and the second input signal;
- and
- a subtractor configured to calculate a difference between the counted value and a set value representing a predetermined ratio of the frequencies of the first input signal and the second input signal.
A PLL circuit including a phase comparator to control an output signal of a variable frequency oscillator, a reference signal of a predetermined frequency is a first input signal, and one of an output signal and a divided signal of the output signal from the variable frequency oscillator is a second input signal,
- wherein the phase comparator for comparing the first input signal and the second input signal, comprising:
- a generator configured to generate a load signal at each rising edge or each falling edge of the first input signal;
- and
- a counter configured to count the second input signal at each interval determined by the load signal, to calculate a difference between a counted value and a set value representing a predetermined ratio of frequencies of the first input signal and the second input signal, and to integrate the difference, an integrated value represents a phase difference of the frequencies of the first input signal and the second input signal.
A PLL circuit including a phase comparator to control an output signal of a variable frequency oscillator, a reference signal of a predetermined frequency is a first input signal, and one of an output signal and a divided signal of the output signal from the variable frequency oscillator is a second input signal,
- wherein the phase comparator for comparing the first input signal and the second input signal, comprising:
- a counter configured to count the second input signal at each rising edge or each falling edge of the first input signal, to calculate a difference between a counted value and a set value of an integer part of a predetermined ratio of frequencies of the first input signal and the second input signal, and to integrate the difference as a digital value;
- an integrator configured to integrate a set value of a decimal part of the predetermined ratio of frequencies of the first input signal and the second input signal;
- and
- a subtractor configured to calculate a difference between the digital value from said counter and an integrated value from said integrator, the difference represents a phase difference of the frequencies of the fist input signal and the second input signal.
A PLL circuit including a phase comparator to control an output signal of a variable frequency oscillator, a reference signal of a predetermined frequency is a first input signal, and one of an output signal and a divided signal of the output signal from the variable frequency oscillator is a second input signal,
- wherein the phase comparator for comparing the first input signal and the second input signal, comprising:
- a counter configured to count the second input signal at each rising edge or each falling edge of the first input signal, and to output a counted value as a digital value representing a ratio of frequencies of the first input signal and the second input signal;
- a converter configured to convert a non-integer digital set value as a predetermined ratio of the frequencies of the first input signal and the second input signal to a sequence of integer digital values whose average value coincides with the digital set value;
- and
- a subtractor configured to calculate a difference between the counted value output from said counter and the integer digital values output from said converter.
A PLL circuit including a phase comparator to control an output signal of a variable frequency oscillator, a reference signal of a predetermined frequency is a first input signal, and one of an output signal and a divided signal of the output signal from the variable frequency oscillator is a second input signal,
- wherein the phase comparator for comparing the first input signal and the second input signal, comprising:
- a converter configured to convert a non-integer digital set value as a predetermined ratio of frequencies of the first input signal and the second input signal to a sequence of integer digital values whose average value coincides with the digital set value;
- and
- a counter configured to count the second input signal at each rising edge or each falling edge of the first input signal, to calculate a difference between a counted value and the integer digital values, and to integrate the difference, an integrated value represents a phase difference of the first input signal and the second input signal.
Dependencies are inferred from the claim text.