Clock logic domino circuits for high-speed and energy efficient microprocessor pipelines
AssigneeMosaid Technologies Incorporated
InventorsRaymond Jit-Hung Sung, Duncan George Elliott
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Abstract
A systematic method for single-rail domino logic circuits is provided, in which inverting and non-monotonic logic functions can be integrated into a pipelined system with almost zero overhead. This logic family, called Clock Logic (CL)-domino is functionally complete while tolerating skew and minimizing the number of clock phases that must be distributed. Simulation results for a CL-domino ALU at 1-GHz under high skew (1-FO4) conditions, shows a power reduction of 41% over the same ALU implemented in dual-rail skew-tolerant domino logic. This power reduction incurs no performance penalty over dual-rail techniques, although in some cases additional design effort is required.
Claims12
A single-rail multi-gate domino logic circuit driven by a multi-phase clock, comprising:
- a first dynamic logic gate having an evaluate clock logic circuit comprising at least first and second transistors driven by respective separate phases of the multi-phase clock.
A single-rail domino circuit driven in accordance with a multi-phase clock, comprising:
- a plurality of logic phases connected in series, each logic phase being associated with a respective current clock phase and comprising at least one dynamic logic gate;
- a respective evaluate clock logic circuit connected to control an evaluate cycle of each dynamic logic gate, the evaluate clock logic circuit comprising respective first and second transistors connected to receive the respective current clock phase and an adjacent clock phase, such that overlap between a precharge cycle of a first logic phase and an evaluation cycle of an adjacent logic phase is prevented.
Dependencies are inferred from the claim text.