Domino circuit topology
AssigneeIntel Corporation
InventorsHans L. Yeager, Scott E. Siers, Brian T. Ormson
Life of this patent
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Abstract
A domino circuit topology that includes a dynamic circuit, logic circuit, and static circuit. The domino circuit includes a dynamic circuit, logic circuit, and static circuit coupled through a central node. The dynamic circuit includes a pre-charge circuit and a keeper circuit for pre-charging the central node and keeping the central node at its current voltage level. The static circuit provides a static output for the domino circuit. The logic circuit provides logical functions for input signals. In addition, the domino circuit can include an isolation transistor coupled between the central node and the logic circuit.
Claims27
A circuit, comprising:
- a dynamic circuit that pre-charges a node;
- a logic circuit coupled to the dynamic circuit through the node, the logic circuit performs a logic operation;
- and
- a transistor coupled between the logic circuit and the node.
A system comprising:
- a die comprising a microprocessor;
- and
- an off-die component in communication with the microprocessor;
- wherein the microprocessor comprises:
- a dynamic circuit that pre-charges a node;
- a logic circuit coupled to the dynamic circuit through the node, the logic circuit performs a logic operation;
- a transistor coupled between the logic circuit and the node;
- and
- a static circuit coupled to the node and an output, the static circuit holds the output in a static state.
A domino circuit topology, comprising:
- a logic circuit that performs a logic operation;
- a first transistor coupled between a first voltage source and a node, the first transistor coupling the first voltage source to the node during a first phase;
- a second transistor coupled between the first voltage source and the node, the second transistor coupling the first voltage source to the node during a second phase;
- and
- a third transistor coupled between the logic circuit and the node, the third transistor coupling the logic circuit to the node during the second phase.
Dependencies are inferred from the claim text.