Optimization of routing layers and board space requirements for ball grid array package implementations including single and multi-layer routing

A method for designing a land pattern for mating an integrated circuit device to a printed circuit board, the method comprising the steps of:

• determining a number of required pads;
• selecting a land pattern to yield the required pads;
• determining a number of required perimeter routing channels;
• and
• optimizing a size of the land pattern to yield the required perimeter routing channels, said optimizing step including under populating at least one perimeter edge of the land pattern.

A printed circuit board, comprising:

• a first layer that comprises a substrate material;
• a plurality of conductive features on a surface of the first layer, said conductive features including a first plurality of conductive pads arranged in a first array of rows and columns configured to receive mounting thereon of an integrated circuit device;
• a second layer that comprises a substrate material;
• a second plurality of conductive pads arranged in a second array of rows and columns on a surface of the second layer, wherein said second array includes fewer rows and columns than said first array;
• and
• a plurality of conductive vias through the printed circuit board that electrically couple at least a portion of said first plurality of conductive pads to corresponding conductive pads of said second plurality of conductive pads,
• wherein at least one edge of a perimeter of said first array is not fully populated with conductive pads, whereby spaces created in said at least one edge by missing conductive pads create additional routing channels for signals from conductive pads within said first array to be routed external to said first array through said at least one edge.

A printed circuit board, comprising:

• a plurality of layers that comprise a substrate material;
• a plurality of conductive features on a surface of a first layer of the plurality of layers, said conductive features including a first plurality of conductive pads arranged in a first array of rows and columns configured to receive mounting thereon of an integrated circuit device;
• a plurality of conductive pads arranged in an array of rows and columns on a surface of each subsequent layer of the plurality of layers, wherein said array on a subsequent layer of the plurality of layers includes fewer rows and columns than said array on a preceding layer;
• and
• a plurality of conductive vias through the printed circuit board that electrically couple at least a portion of said first plurality of conductive pads to corresponding conductive pads of said plurality of conductive pads of each subsequent layer of the plurality of layers,
• wherein at least one edge of a perimeter of said first array is not fully populated with conductive pads, whereby spaces created in said at least one edge by missing conductive pads create additional routing channels for signals from conductive pads within said first array to be routed external to said first array through said at least one edge.

A method for designing a land pattern for mating an integrated circuit device to a printed circuit board, the method comprising:

• (1) determining a number of required pads;
• (2) determining a number of layers of the printed circuit board to have routing channels;
• (3) selecting a land pattern to yield the required pads;
• (4) determining a number of required perimeter routing channels for an array of conductive pads on each layer of the determined number of layers;
• and
• (5) optimizing a size of the land pattern to yield the required perimeter routing channels in each layer, said optimizing step including under populating at least one perimeter edge on at least one layer.